IP Library Granted Patent US 10,572,185
Granted Patent B2
US 10,572,185 · App. 15/995,590 · Granted Feb 25, 2020

Non-volatile storage system with command replay

Inventors: Judah Gamliel Hahn (Ofra, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0613G06F3/0656G06F3/0679G06F9/4401
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Quick Facts
Patent No.
US 10,572,185
App. No.
15/995,590
Granted
Feb 25, 2020
Kind
B2
Abstract

A memory system includes a non-volatile memory and a controller connected to the non-volatile memory. The controller is configured to receive a set of commands from a host during a first host startup sequence, write the set of commands in the non-volatile memory, and in response to receiving an indicator from the host, execute the set of commands written in the non-volatile memory during a second host startup sequence.

Claims (62)

1. A memory system, comprising:

non-volatile memory configured to store a plurality of sets of commands, each set of commands having a corresponding indicator; and

a controller connected to the non-volatile memory, wherein the controller is configured to:

execute an individual set of commands for memory operations,

write a copy of the individual set of commands to the non-volatile memory,

receive an individual indicator from the host,

select the individual set of commands from the plurality of sets of commands in response to receiving the individual indicator associated with the individual set of commands,

read and execute the individual set of commands stored in the non-volatile memory during a host startup sequence, and

inform the host that the individual set of commands is executed.

2. The memory system of claim 1 , wherein:

the controller is configured to receive the individual set of commands from the host during a first host startup sequence, the individual set of commands including at least one read command directed to host startup data written in the non-volatile memory; and

the controller is configured to, in response to receiving the individual indicator, execute the individual set of commands written in the non-volatile memory during the second host startup sequence including the at least one read command directed to host startup data written in the non-volatile memory.

3. The memory system of claim 1 wherein, the controller is configured to receive the individual set of commands from the host through a host interface during a recorded host startup sequence and to subsequently execute the individual set of commands from the non-volatile memory during the host startup sequence without receiving the set of commands from the host through the host interface during the host startup sequence.

4. The memory system of claim 3 , wherein:

the recorded host startup sequence has a first host startup time and the host startup sequence has a second host startup time that is less than the first host startup time.

5. The memory system of claim 1 , wherein:

the individual set of commands includes one or more read commands specifying source addresses in the non-volatile memory and destination addresses in a host memory; and

the controller is configured to execute the individual set of commands from the non-volatile memory by reading specified data from the source addresses in the non-volatile memory and writing the specified data to the destination addresses in the host memory.

6. The memory system of claim 5 wherein the destination addresses in the host memory are located in a Host Memory Buffer.

7. The memory system of claim 1 , wherein the controller is further configured to:

receive the individual set of commands from a host during a recorded host startup sequence; and

write the individual set of commands in the non-volatile memory.

8. The memory system of claim 1 , wherein:

each set of commands includes one or more read commands from a host specifying a source address in the non-volatile memory and a destination address in a host memory, one or more pointers, one or more doorbells, and one or more time stamps.

9. The memory system of claim 1 , wherein:

the non-volatile memory and the controller are part of a solid state drive; and

the controller is further configured to implement a NVM Express interface with the host.

10. The memory system of claim 1 , wherein the controller is further configured to:

store the individual set of commands in a log in the memory system prior to writing the set of commands in the non-volatile memory; and

write the individual set of commands to the non-volatile memory from the log.

11. The memory system of claim 10 , wherein the controller is further configured to:

store, in the log, timing information for the individual set of commands; and

use the timing information to execute the individual set of commands from the non-volatile memory.

12. A method, comprising:

executing in a solid state drive a plurality of sets of commands received from a host connected to the solid state drive, each set of the plurality of sets of commands specifying respective source addresses in non-volatile memory and destination addresses in a host memory;

saving the plurality of sets of commands in a non-volatile memory in the solid state drive;

subsequently receiving an indicator in the solid state drive from the host;

identifying a corresponding set of commands corresponding to the indicator from the plurality of sets of commands;

the solid state drive reading and executing the corresponding set of commands saved in the non-volatile memory including copying data from the respective source addresses in the non-volatile memory to the respective destination addresses in the host memory; and

informing the host that the set of commands is executed.

13. The method of claim 12 , wherein the corresponding set of commands are received from the host during a first host startup sequence and the indicator is subsequently received from the host during a second host startup sequence.

14. The method of claim 13 , wherein the second host startup sequence is faster than the first host startup sequence.

15. The method of claim 13 , further comprising:

saving one or more additional sets of commands received from the host during one or more additional host startup sequences in the non-volatile memory and subsequently executing the one or more additional sets of commands in response to one or more additional indicators from the host.

16. The method of claim 15 , wherein the destination addresses in the host memory are located in a Host Memory Buffer and data from the source addresses in the non-volatile memory are copied to the destination addresses in the Host Memory Buffer.

17. An apparatus, comprising:

a host interface configured to be connected to a host;

a memory interface configured to be connected to non-volatile memory; and

a processor connected to the host interface and the memory interface, wherein the processor is configured to:

execute a sequence of commands for memory operations,

receive an indicator from the host;

identify the sequence of commands corresponding to the indicator from a plurality of sequences of commands in the non-volatile memory;

replay the sequence of commands by writing a copy of the sequence of commands to a non-volatile memory via the memory interface and subsequently reading and executing the copy of the sequence of commands from the non-volatile memory; and

inform the host that the sequence of commands is executed.

18. The apparatus of claim 17 , wherein the processor is further configured to receive the sequence of commands from the host during a first host startup sequence and to subsequently read and execute the copy of the sequence of commands from the non-volatile memory during a second host startup sequence.

19. A solid state drive, comprising:

a non-volatile memory die; and

a controller connected to the non-volatile memory die and configured to communicate with a host external to the solid state drive, the controller comprising:

a command log configured to store a plurality of sequences of commands including a sequence of commands received from a host during a first host startup sequence in response to a first host indicator,

means for identifying the sequence of commands from the plurality of sequences of commands in response to a second indicator directed to the sequence of commands; and

means for replaying the sequence of commands during a second host startup sequence in response to the second host indicator by reading the sequence of commands from the command log, writing the sequence of commands read to the non-volatile memory die, executing, at the controller, the sequence of commands from the non-volatile memory die, and informing the host that the sequence of commands is executed.

20. The solid state drive of claim 19 , wherein the sequence of commands includes one or more read commands specifying source addresses in the non-volatile memory die and destination addresses in a host memory.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2018
From: HAHN, JUDAH GAMLIEL; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045977/0495 →
Continuity (1)
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