IP Library Granted Patent US 12,566,572
Granted Patent B2
US 12,566,572 · App. 18/533,565 · Granted Mar 3, 2026

Method for optimizing interface training on a storage device

Inventors: Mohith Kumar N (Bangalore, IN); Vishal Sharma (Bangalore, IN)
Assignee: SANDISK TECHNOLOGIES, INC.
G06F3/0658G06F3/0619G06F3/0679
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Quick Facts
Patent No.
US 12,566,572
App. No.
18/533,565
Granted
Mar 3, 2026
Kind
B2
Abstract

A storage device optimizes interface training between a controller and a memory device. The memory device includes at least one die on which data is stored. The controller categorizes process, voltage, and temperature (PVT) values into zones and executes an initial calibration on each zone using categorized values assigned to each zone. The controller obtains calibration data for the zones from the initial calibration and stores the calibration data. When the controller determines that an interface training is triggered, the controller performs a subsequent calibration. During the subsequent calibration, the controller retrieves the calibration data and applies the retrieved calibration data to align a data signal with a clock signal and to perform normal operations on the storage device at a current PVT setting.

Claims (32)

1 . A storage device optimizes interface training between a controller and a memory device, the storage device comprises:

a memory device including at least one die on which data is stored; and

a controller to:

categorize process, voltage, and temperature (PVT) values into zones, wherein a zone represents a unique PVT criterion for which associated calibration values include an optimal data signal, clock signal, and read enable offset for aligning data signal with clock signal,

execute an initial calibration using categorized values, obtain calibration data for the zones from the initial calibration, and store the calibration data, and

determine that an interface training is triggered and perform a subsequent calibration including retrieving the calibration data and applying retrieved calibration data to align the data signal with the clock signal and perform normal operations on the storage device at a current PVT setting.

2 . The storage device of claim 1 , wherein during the subsequent calibration, the controller identifies current PVT values under which the storage device is operating, retrieves the calibration data in a zone that includes the current PVT values, and applies an optimal data signal, clock signal, and read enable offset associated with the zone to perform normal operations on the storage device.

3 . The storage device of claim 1 , wherein the optimal data signal, clock signal, and read enable offset includes a duty cycle correction read enable offset, a read data signal and clock signal offset, and a write data signal and clock signal offset,

wherein during the subsequent calibration, the controller retrieves the duty cycle correction read enable offset, the read data signal and clock signal offset, and the write data signal and clock signal offset and applies retrieved offsets to align the data signal and the clock signal during normal operations on the storage device.

4 . The storage device of claim 1 , wherein the controller categorizes a range of temperatures under which the storage device may operate into the zones, with each zone including a subset temperature range.

5 . The storage device of claim 1 , wherein when executing the initial calibration, the controller uses varying temperature values and maintains a fixed set of voltage values and a fixed set of process values across the zones.

6 . The storage device of claim 1 , wherein the controller executes the initial calibration in more than one settings in a zone, with each setting including a different data signal, clock signal, and read enable shift value and the controller selects an optimal data signal, clock signal, and read enable offset for the data signal, clock signal, and read enable shift value resulting in a lowest bit error rate.

7 . The storage device of claim 1 , wherein the subsequent calibration includes a ZQ calibration.

8 . The storage device of claim 1 , wherein the controller stores the calibration data in a non-volatile memory.

9 . A method on a storage device for optimizing interface training between a controller and a memory device including at least one die on which data is stored, the controller executes the method comprising:

categorizing process, voltage, and temperature (PVT) values into zones, wherein a zone represents a unique PVT criterion for which associated calibration values include an optimal data signal, clock signal, and read enable offset for aligning data signal with clock signal;

executing an initial calibration using categorized values and obtaining calibration data for the zones from the initial calibration;

storing the calibration data;

determining that an interface training is triggered; and

performing a subsequent calibration including retrieving the calibration data and applying retrieved calibration data to align the data signal with the clock signal and perform normal operations on the storage device at a current PVT setting.

10 . The method of claim 9 , wherein performing the subsequent calibration includes identifying current PVT values under which the storage device is operating, retrieving the calibration data associated with a zone and the current PVT values, and applying an optimal data signal, clock signal, and read enable offset associated with the zone to perform normal operations on the storage device.

11 . The method of claim 9 , wherein executing the initial calibration includes generating an optimal data signal, clock signal, and read enable offset for aligning the data signal with the clock signal and storing the optimal data signal, clock signal, and read enable offset for a zone in a non-volatile memory, wherein the zone represents a unique PVT criterion.

12 . The method of claim 11 , wherein the optimal data signal, clock signal, and read enable offset includes a duty cycle correction read enable offset, a read data signal and clock signal offset, and a write data signal and clock signal offset, wherein performing the subsequent calibration includes retrieving and applying the duty cycle correction read enable offset, the read data signal and clock signal offset, and the write data signal and clock signal offset to align the data signal and the clock signal and perform normal operations on the storage device.

13 . The method of claim 9 , wherein the categorizing further comprises categorizing a range of temperatures under which the storage device may operate into the zones, with each zone including a subset temperature range.

14 . The method of claim 9 , wherein when executing the initial calibration, the method comprises using varying temperature values and maintaining a fixed set of voltage values and a fixed set of process values across the zones.

15 . The method of claim 9 , executing the initial calibration includes further comprises executing the initial calibration in more than one setting in a zone, with each setting including a different data signal, clock signal, and read enable shift value and selecting an optimal data signal, clock signal, and read enable offset for the data signal, clock signal, and read enable shift value resulting in a lowest bit error rate.

16 . The method of claim 9 , wherein performing the subsequent calibration includes executing a ZQ calibration.

17 . A method on a storage device for optimizing interface training between a controller and a memory device including at least one die on which data is stored, the controller executes the method comprising:

categorizing process, voltage, and temperature (PVT) values into zones,

executing an initial calibration using categorized PVT values and storing calibration data obtained from the initial calibration for the zones,

determining that an interface training is triggered; and

executing a subsequent calibration including identifying current PVT values under which the storage device is operating, retrieving the calibration data for a zone associated with the current PVT values, and applying an optimal data signal, clock signal, and read enable offset from retrieved calibration data to perform normal operations on the storage device under the current PVT values.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0284 →
PATENT COLLATERAL AGREEMENT (DDTL) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2023
From: KUMAR N, MOHITH; SHARMA, VISHAL
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 065809/0983 →
Continuity (1)
Related Publication 20250190142A1 · Jun 12, 2025
References Cited (11)
US 6670821B2 · Ajit · 2003 [cited by examiner]
US 7157932B2 · El-Kik · 2007 [cited by examiner]
US 7432731B2 · Bains · 2008 [cited by examiner]
US 10216420B1 · Kannan · 2019 [cited by applicant]
US 10310999B2 · Zerbe · 2019 [cited by applicant]
US 10949094B2 · Lee · 2021 [cited by applicant]
US 11082036B2 · Marko · 2021 [cited by applicant]
US 11237579B2 · He · 2022 [cited by examiner]
US 20170123446A1 · Siddula · 2017 [cited by examiner]
US 20200201705A1 · Kim · 2020 [cited by examiner]
US 20210081109A1 · Wang · 2021 [cited by examiner]