Cell block allocation for hybrid dual write
Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.
1. An apparatus comprising:
a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks; and
a hybrid writing component comprising:
a single level writing circuit configured to write data to the plurality of single level cell blocks;
a multi level writing circuit configured to copy the data from the plurality of single level cell blocks to the plurality of multi level cell blocks;
an allocation circuit configured to allocate an entire first single level cell block of the plurality of single level cell blocks to a first stream in response to a first multi level cell block of the plurality of multi level cell blocks being allocated to the first stream, an entire second single level cell block of the plurality of single level cell blocks to a second stream in response to a second multi level cell block of the plurality of multi level cell blocks being allocated to the second stream, an entire third single level cell block of the plurality of single level cell blocks to a third multi level cell block of the plurality of multi level cell blocks, and a fourth single level cell block of the plurality of single level cell blocks to be appended to the first multi level cell block, and the second multi level cell block, and the third multi level cell block;
an indexing circuit that records, in an index, allocation of the first single level cell block, the second single level cell block, the third single level cell block, and the fourth single level cell block before the first stream and the second stream are transferred based on the allocation; and
a control circuit that controls the data to be copied based on the allocation, wherein the control circuit controls:
the entire first single level cell block to be copied to the first multi level cell block based on the allocation;
the entire second level cell block to be copied to the second multi level cell block based on the allocation;
the entire third level cell block to be copied to the third multi level cell block based on the allocation; and
different portions of the fourth single level cell block to be appended to each of the first multi level cell block, the second multi level cell block, and the third multi level cell block as a result of the first multi level cell block, the second multi level cell block, and the third multi level cell block not being filled respectively by the entire first single level cell block, the entire second single level cell block, and the entire third single level cell block.
2. The apparatus of claim 1 , wherein the hybrid writing component further comprises a replay circuit that returns the memory device to a state the memory device was in prior to a power cycle occurring.
3. The apparatus of claim 2 , wherein the replay circuit directs the allocation circuit to allocate additional single level cell blocks of the plurality of single level cell blocks to the first stream based on data stored in the multi level cell block.
4. The apparatus of claim 3 , wherein the replay circuit scans a buffer to determine a number of the additional single level cell blocks to allocate to the first stream.
5. The apparatus of claim 2 , wherein the replay circuit directs the allocation circuit to allocate one or more single level cell blocks of the plurality of single level cell blocks to the second stream.
6. The apparatus of claim 1 , wherein a portion of each single level cell block of the plurality of single level cell blocks is unavailable for storing data.
7. The apparatus of claim 6 , wherein the portion comprises 16 pages.
8. The apparatus of claim 1 , further comprising a verification circuit that verifies the data stored on the plurality of multi level cell blocks.
9. The apparatus of claim 8 , further comprising a recycling circuit that reuses single level cell blocks of the plurality of single level cell blocks corresponding to verified multi level cell blocks of the plurality of multi level cell blocks.
10. A method comprising:
writing information to a master index before a first data stream is transferred based on an allocation, wherein the information indicates the allocation of:
a first multi level cell block of a storage device and an entire first single level cell block of the storage device to the first data stream;
a second multi level cell block of the storage device and an entire second single level cell block of the storage device to a second data stream;
an entire third single level cell block of the storage device to a third multi level cell block; and
a fourth single level cell block of the storage device to the first multi level cell block, the second multi level cell block, and the third multi level cell block;
reading the information from the master index in response to detecting a power cycle event of the storage device occurring;
replaying storage events that occur between writing the information to the master index and the power cycle event to put the storage device into a state the storage device was in at a time the power cycle event occurred; and
transferring the first data stream based on the allocation by:
copying the entire first single level cell block to the first multi level cell block based on the allocation;
copying the entire second level cell block to the second multi level cell block based on the allocation;
copying the entire third level cell block to the third multi level cell block based on the allocation; and
appending different portions of the fourth single level cell block to each of the first multi level cell block, the second multi level cell block, and the third multi level cell block as a result of the first multi level cell block, the second multi level cell block, and the third multi level cell block not being filled respectively by the entire first single level cell block, the entire second single level cell block, and the entire third single level cell block.
11. The method of claim 10 , wherein replaying the storage events comprises allocating additional single level cell blocks to the first data stream in response to determining that the additional single level cell blocks were previously allocated after the information was written to the master index.
12. The method of claim 10 , wherein replaying the storage events comprises searching a buffer to determine the storage events that occurred after the information was written to the master index.
13. The method of claim 10 , wherein part of the first single level cell block is not used for storing data.
14. The method of claim 10 , wherein replaying the storage events comprises allocating single level cell blocks to the first data stream and additional data streams based on results from searching a buffer.
15. The method of claim 10 , wherein replaying the storage events comprises reading header information of one or more single level cell blocks to determine a data stream corresponding to the one or more single level cell blocks.
16. An apparatus comprising:
means for storing index information for a plurality of data streams before the plurality of data streams are transferred based on an allocation, wherein the index information comprises information that indicates the allocation of:
a first multi level cell block and an entire first single level cell block to a first data stream of the plurality of data streams;
a second multi level cell block and an entire second single level cell block to a second data stream of the plurality of data streams;
an entire third single level cell block to a third multi level cell block; and
a fourth single level cell block to the first multi level cell block, the second multi level cell block, and the third multi level cell block;
means for replaying storage events that occur between a first time at which the index information is stored and a second time at which a power cycle occurs at a memory device; and
means for transferring the first data stream based on the allocation by:
copying the entire first single level cell block to the first multi level cell block based on the allocation;
copying the entire second level cell block to the second multi level cell block based on the allocation;
copying the entire third level cell block to the third multi level cell block based on the allocation; and
appending different portions of the fourth single level cell block to each of the first multi level cell block, the second multi level cell block, and the third multi level cell block as a result of the first multi level cell block, the second multi level cell block, and the third multi level cell block not being filled respectively by the entire first single level cell block, the entire second single level cell block, and the entire third single level cell block.
17. The apparatus of claim 16 , further comprising means for allocating a single level cell block and a multi level cell block to a data stream.
18. The apparatus of claim 16 , further comprising means for determining the storage events that occur between the first time and the second time.