Intelligent memory wear leveling
A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.
1. A data storage device, comprising:
a non-volatile memory device including a memory block; and
a controller coupled to the non-volatile memory device and configured to:
receive a cycle operation request;
perform a wear-level mitigation operation in response to receiving the cycle operation request, wherein to perform the wear-level mitigation operation, the controller is further configured to:
determine whether the memory block is in a first read state or a second read state;
perform the requested cycle operation and increment a cycle count of the memory block by a first value in response to determining that the memory block is in the first read state; and
perform the requested cycle operation of the memory block and increment the cycle count of the memory block by a second value in response to determining that the memory block is in the second read state; and
wherein the first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.
2. The data storage device of claim 1 , wherein the first value is 1 and the second value is a value greater than 1.
3. The data storage device of claim 2 , wherein the second value is 1.2.
4. The data storage device of claim 1 , wherein the non-volatile memory device includes wear-level mitigation circuitry, and wherein, to perform the wear-level mitigation operation, the controller is further configured to:
determine whether the memory block is in the first read state or the second read state,
perform the requested cycle operation and increment a cycle count of the memory block by a value of 1 in response to determining that the memory block is in the first read state;
control the wear-level mitigation circuitry to force the memory block from the second read state to the first read state; and
perform the requested cycle operation of the memory block and increment the cycle count of the memory block by 1 in response to controlling the wear-level mitigation circuitry to force the memory block from the second read state to the first read state.
5. The data storage device of claim 4 , wherein the wear-level mitigation operation is performed based on a temperature of the data storage device being below a predetermined threshold.
6. The data storage device of claim 1 , wherein the non-volatile memory device includes a wear-level mitigation circuitry, and
wherein, to perform the wear-level mitigation operation, the controller is further configured to:
control the wear-level mitigation circuitry to force the memory block to the first read state;
perform the requested cycle operation of the memory block in response to controlling the wear-level mitigation circuitry to force the memory block to the first read state; and
increment the cycle count of the memory block.
7. The data storage device of claim 1 , wherein the controller is further configured to determine the wordline voltage based on one or more of a period of time since a read operation of the memory block was last performed and a temperature of the data storage device.
8. The data storage device of claim 7 , wherein the controller is further configured to determine the memory block is in the second read state when the wordline voltage associated with the memory block is equal to or greater than four volts (V).
9. A method performed by a controller coupled to a non-volatile memory device, the method comprising:
receiving a cycle operation request; and
performing a wear-level mitigation operation in response to receiving the cycle operation request,
wherein performing the wear-level mitigation operation comprises:
determining whether the memory block is in a first read state or a second read state,
performing the requested cycle operation of the memory block and increment a cycle count of the memory block by a first value in response to determining that the memory block is in the first read state; and
performing the requested cycle operation of the memory block and increment the cycle count of the memory block by a second value in response to determining that the memory block is in the second read state, and
wherein the first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.
10. The method of claim 9 , wherein the first value is 1 and the second value is a value greater than 1.
11. The method of claim 10 , wherein the second value is 1.2.
12. The method of claim 9 , wherein the non-volatile memory device includes a wear-level mitigation circuitry, and wherein, performing the wear-level mitigation operation further comprises:
determining whether the memory block is in the first read state or the second read state;
performing the requested cycle operation and incrementing a cycle count of the memory block by a value of 1 in response to determining that the memory block is in the first read state;
controlling the wear-level mitigation circuitry to force the memory block from the second read state to the first read state; and
performing the requested cycle operation of the memory block and incrementing the cycle count of the memory bock by 1 in response to controlling the wear-level mitigation circuitry to force the memory block to the first read state.
13. The method of claim 12 , wherein the wear-level mitigation operation is performed based on one or more a cycle count of the memory block and a temperature of the data storage device.
14. The method of claim 9 , wherein the non-volatile memory device includes a wear-level mitigation circuitry, and wherein performing the wear-level mitigation operation comprises:
controlling the wear-level mitigation circuitry to force the memory block to the first read state;
performing the requested cycle operation of the memory block in response to controlling the wear-level mitigation circuitry to force the memory block to the first read state; and
incrementing the cycle count of the memory block.
15. An apparatus, comprising:
means for receiving a request to cycle a memory block, wherein the memory block is within a non-volatile memory device of a data storage device; and
means for performing a wear-level mitigation operation in response to receiving the cycle operation request,
whereinthe means to perform the wear-level mitigation operation is further configured to:
determine whether the memory block is in a first read state or a second read state;
perform the requested cycle operation of the memory block and increment a cycle count of the memory block by a first value in response to determining that the memory block is in the first read state;
perform the requested cycle operation of the memory block and increment the cycle count of the memory block by a second value in response to determining that the memory block is in the second read state, and
wherein the first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.
16. The apparatus of claim 15 , wherein the first value is 1 and the second value is a value greater than 1.
17. The apparatus of claim 16 , wherein the second value is 1.2.
18. The apparatus of claim 15 , wherein the non-volatile memory device includes a wear-level mitigation circuitry, and wherein the means to perform the wear-level mitigation operation is further configured to:
determine whether the memory block is in the first read state or the second read state,
perform the requested cycle operation and increment a cycle count of the memory block by a value of 1 in response to determining that the memory block is in the first read state;
control the wear-level mitigation circuitry to force the memory block from the second read state to the first read state; and
perform the requested cycle operation of the memory block and increment the cycle count of the memory block by 1 in response to controlling the wear-level mitigation circuitry to force the memory block to the first read state.
19. The apparatus of claim 18 , wherein the wear-level mitigation operation is performed based on a temperature of the data storage device being below a predetermined threshold.
20. The apparatus of claim 15 , wherein the non-volatile memory device includes a wear-level mitigation circuitry, and wherein the means to perform the wear-level mitigation operation is further configured to:
control the wear-level mitigation circuitry to force the memory block to the first read state;
perform the requested cycle operation of the memory block in response to controlling the wear-level mitigation circuitry to force the memory block to the first read state; and
increment the cycle count of the memory block.