IP Library Granted Patent US 12,038,853
Granted Patent B2
US 12,038,853 · App. 17/726,762 · Granted Jul 16, 2024

Reducing link up time in PCIe systems

Inventor: Shuli Shmaya (Ks, IL)
Assignee: Western Digital Technologies, Inc.
G06F13/102
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Quick Facts
Patent No.
US 12,038,853
App. No.
17/726,762
Granted
Jul 16, 2024
Kind
B2
Abstract

The present disclosure generally relates to reducing link-up time between an upstream device and a downstream device. Rather than re-coordinating the link between devices each time, knowledge gained from a previous link-up is used to speed up the link-up. Typically, when both the upstream device and the downstream device have not changed, then the coefficient values for downstream port (DSP) transmission (Tx) equilibrium (EQ) that resulted in a desired bit error rate (BER) should not have changed either. Hence, rather than exchanging coefficients, the previous values can be reused with confidence eliminating the need to exchange coefficients. In so doing, the link-up process is much faster and system resources are not wasted on unnecessary coefficient exchanges.

Claims (15)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

send a speed change request to a host device;

determine that optimal channel setup values exist for link-up between the host device and the data storage device, wherein the optimal channel setup values are calculated prior to sending the speed change request, and wherein the optimal channel setup values correspond to channel setup values associated with the requested speed change; and

perform channel setup using the optimal channel setup values.

2. The data storage device of claim 1 , wherein the controller is further configured to send the optimal channel setup values to the host device.

3. The data storage device of claim 1 , wherein the optimal channel setup values correspond to a bit error rate of 10 −12 or better.

4. The data storage device of claim 1 , wherein the controller is further configured to store the optimal channel setup values in a table.

5. The data storage device of claim 4 , wherein the table is preloaded into the controller.

6. The data storage device of claim 4 , wherein the table is dynamic.

7. The data storage device of claim 1 , wherein the controller is configured to send the speed change request when the data storage device is in a L0 state.

8. The data storage device of claim 1 , wherein the optimal channel setup values correspond to speeds of 8 GT/s or greater.

9. The data storage device of claim 1 , wherein the controller is configured to receive presets values from the host device.

10. The data storage device of claim 1 , wherein the controller is further configured to verify reliable channel operation of a BER that is less than 10 −4 .

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2022
From: SHMAYA, SHULI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059678/0189 →
Continuity (1)
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