Transistor threshold voltage maintenance in 3D memory
Techniques are provided for maintaining threshold voltages of non-data transistors in a memory device. The memory device has a stack comprising alternating horizontal conductive layers and horizontal dielectric layers. A control circuit is configured to test a threshold voltage criterion of non-data transistors in response to a trigger condition being met with respect to an erase of a data memory cells in a first tier of the stack. The control circuit is configured move valid data out of a data memory cells in a second tier of the stack in response to a determination that the threshold voltage criterion is not met. The control circuit is configured to adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells such that the threshold voltage criterion is met.
1. An apparatus comprising:
a memory interface configured to be connected to non-volatile memory; and
a processor circuit connected to the memory interface, the processor circuit configured to:
test a threshold voltage criterion of non-data transistors associated with memory cells that reside in a stack in the non-volatile memory, the test in response to a trigger condition being met with respect to an erase of a first set of data memory cells that reside in a first tier of the stack, the memory cells including a second set of data memory cells that reside in a second tier of the stack;
move valid data out of the second set of data memory cells to another location in the non-volatile memory in response to a determination that the threshold voltage criterion is not met; and
adjust threshold voltages of the non-data transistors after moving the valid data out of the second set of data memory cells to the other location such that the threshold voltage criterion is met for the non-data transistors.
2. The apparatus of claim 1 , wherein:
the trigger condition is based on a count of a number of erases of the first set of data memory cells; and
the processor circuit is further configured to erase the first set of data memory cells while maintaining valid data in the second set of data memory cells when the trigger condition is not met.
3. The apparatus of claim 2 , wherein:
the trigger condition is further based on whether the threshold voltage criterion of the non-data transistors has been tested in response to an erase of the second set of data memory cells.
4. The apparatus of claim 2 , wherein the processor circuit is further configured to:
store information that indicates that the threshold voltage criterion of the non-data transistors has been tested in response to the trigger condition being met with respect to the erase of the first set of data memory cells; and
skip a test of the threshold voltage criterion of the non-data transistors when a count of a number of erases of the second set of data memory cells reaches a threshold that indicates the test should otherwise be performed if the stored information indicates that the threshold voltage criterion of the non-data transistors has been tested in response to the trigger condition being met with respect to the erase of the first set of data memory cells.
5. The apparatus of claim 1 , wherein:
the memory cells are part of a group of NAND strings;
the apparatus further comprises a plurality of bit lines;
the non-data transistors comprise a select transistor on each NAND string connected to one of the bit lines, each select transistor having a control terminal;
the apparatus further comprises a select line connected to the control terminal of each select transistor; and
to test the threshold voltage criterion the processor circuit is further configured to determine whether more than an allowed number of the select transistors have a threshold voltage outside of a target range.
6. The apparatus of claim 1 , wherein:
the memory cells are part of a group of NAND strings;
the apparatus further comprises a source line;
the non-data transistors comprise a select transistor on each NAND string connected to the source line, each select transistor having a control terminal;
the apparatus further comprises a select line connected to the control terminal of each select transistor; and
to test the threshold voltage criterion the processor circuit is further configured to determine whether more than an allowed number of the select transistors have a threshold voltage outside of a target range.
7. The apparatus of claim 1 , wherein:
the memory cells are part of a group of NAND strings;
the non-data transistors comprise a dummy memory cell transistor on each NAND string; and
to test the threshold voltage criterion the processor circuit is further configured to determine whether more than an allowed number of the dummy memory cell transistors have a threshold voltage outside of a target range.
8. The apparatus of claim 1 , wherein:
the memory cells are part of a group of NAND strings;
the non-data transistors comprise a first select transistor at a first end of each NAND string and a second select transistor at a second end of each NAND string, the first set of data memory cells is arranged between the first select transistor and the second set of data memory cells, the second set of data memory cells is arranged between the first set of data memory cells and the second select transistor.
9. The apparatus of claim 8 , wherein:
the data transistors further comprise a third set of data memory cells arranged between the second set of data memory cells and the second select transistor; and
the processor circuit is further configured to move valid data out of the third set of data memory cells to another location in response to the determination that the threshold voltage criterion is not met and prior to adjusting the threshold voltages of the non-data transistors such that the threshold voltage criterion is met.
10. A method of operating non-volatile storage, the method comprising:
testing whether a threshold voltage distribution of a set of select transistors for groups of memory cells in a stack in a three-dimensional memory array is outside of a target range, each group of memory cells comprising a first set of data memory cells that reside in a first tier of the stack and a second set of data memory cells that reside in a second tier of the stack, the testing in response to a program/erase count of the first sets of data memory cells exceeding a threshold;
moving valid data out of the second sets of data memory cells to another location in response to a determination that the threshold voltage distribution is outside of the target range; and
adjusting threshold voltages of the set of select transistors after moving the valid data out of the second sets of data memory cells to the other location such that the threshold voltage distribution is within the target range.
11. The method of claim 10 , further comprising:
erasing the first sets of data memory cells while maintaining valid data in the second sets of data memory cells when the program/erase count of the first sets of data memory cells does not exceed the threshold.
12. The method of claim 10 , further comprising:
storing information that indicates that the threshold voltage distribution of the set of select transistors has been tested in response to the program/erase count of the first sets of data memory cells exceeding the threshold; and
skipping a test of the threshold voltage distribution of the set of select transistors when a program/erase count of the second sets of data memory cells reaches a threshold that indicates the test should otherwise be performed if the stored information indicates that the threshold voltage distribution of the set of select transistors has been tested in response to the program/erase count with respect to the erase of the first sets of data memory cells exceeding the threshold.
13. The method of claim 10 , wherein testing the threshold voltage distribution of the set of select transistors comprises:
testing whether more than an allowed number of the set of select transistors have a threshold voltage outside of the target range for the threshold voltage distribution.
14. The method of claim 10 , wherein testing the threshold voltage distribution of the set of select transistors comprises:
testing the threshold voltages of drain side select transistors on a group of NAND strings, each drain side select transistor connected to a different bit line, each drain side select transistor having a control terminal that is connected to the same select line.
15. The method of claim 10 , wherein testing the threshold voltage distribution of the set of select transistors comprises:
testing the threshold voltages of source side select transistors on a group of NAND strings, each source side select transistor connected to a source line, each source side select transistor having a control terminal that is connected to the same select line.
16. A non-volatile memory device, comprising:
a three-dimensional memory array comprising groups memory cells, a first select transistor at a first end of each group, a second select transistor at a second end of each group, each group comprising a first set of data memory cells and a second set of data memory cells, the first set of data memory cells arranged between the first select transistor and the second set of data memory cells, the second set of data memory cells arranged between the first set of data memory cells and the second select transistor; and
a control circuit configured to:
erase the first set of data memory cells while maintaining valid data in the second set of data memory cells when a trigger condition with respect to the erase of the first set of data memory cells is not met;
sense threshold voltages of the first select transistors in response to the trigger condition being met;
move valid data out of the second set of data memory cells to another location in response to a determination that more than an allowed number of the first select transistors have a threshold voltage outside of a target range; and
adjust threshold voltages of the first select transistors after moving the valid data out of the second set of data memory cells to the other location such that no more than the allowed number of the first select transistors have a threshold voltage outside of the target range.
17. The non-volatile memory device of claim 16 , wherein:
the trigger condition is further based on whether the threshold voltages of the first select transistors have been sensed in response to an erase of the second set of data memory cells.
18. The non-volatile memory device of claim 16 , wherein:
the non-volatile memory device further comprises a plurality of bit lines;
the first select transistor associated with a group is connected to a different one of the plurality of bit lines;
each of the first select transistors comprises a control gate; and
the non-volatile memory device further comprises a select line connected to the control gate of each of the first select transistors.
19. The non-volatile memory device of claim 16 , wherein:
the non-volatile memory device further comprises a source line;
the first select transistor associated with a group comprises a control terminal connected to the source line; and
the non-volatile memory device further comprises a select line connected to the control terminal of each first select transistor.
20. The non-volatile memory device of claim 16 , wherein:
each group further comprises a third set of data memory cells arranged between the second set of data memory cells and the second select transistor; and
the control circuit is further configured to move valid data out of the third set of data memory cells to another location in response to the determination that more than the allowed number of the first select transistors have a threshold voltage outside of the target range and prior to adjusting the threshold voltages of the first select transistors.