Granted Patent B2

US 9,342,445 · App. 12/508,531 · Granted May 17, 2016

Abstract

Claims (57)

1. A method of transferring data in a flash storage device, the method comprising:

receiving a select signal from a host, the select signal indicating a selection between a first communication protocol and a second communication protocol;

receiving a first request for a first direct memory access from the host by the flash storage device, the first direct memory access corresponding to at least one of the first communication protocol or the second communication protocol based on the received select signal;

obtaining a predetermined address from a memory in the flash storage device in response to the first request; and

performing the first direct memory access at sequential addresses in flash storage in the flash storage device starting at the predetermined address.

2. The method of claim 1 , further comprising selecting the predetermined address before receiving the first request.

3. The method of claim 1 , wherein performing the first direct memory access comprises:

receiving a data block from the host by the flash storage device;

erasing a storage block in the flash storage device; and

writing the data block to the storage block.

4. The method of claim 1 , wherein performing the first direct memory access comprises:

receiving a plurality of data blocks from the host by the flash storage device; and

storing the plurality of data blocks in the flash storage device.

5. The method of claim 4 , further comprising:

receiving a second request from a host by the flash storage device; and

performing a second direct memory access based on the second request at the predetermined address of the flash storage device, the second direct memory access comprising reading the plurality of data blocks from the flash storage device.

6. The method of claim 5 , wherein the first direct memory access is performed by using the first communication protocol, and wherein the second direct memory access is performed by using the second communication protocol.

7. The method of claim 6 , wherein the first communication protocol is a custom communication protocol and the second communication protocol is a standard communication protocol.

8. The method of claim 6 , wherein the flash storage device receives the first request from a first host and the second request from a second host, the method further comprising:

connecting the first host to the flash storage device before performing the first direct memory access;

disconnecting the first host from the flash storage device after performing first the direct memory access; and

connecting the second host to the flash storage device after disconnecting the first host from the flash storage device.

9. The method of claim 1 , wherein performing the first direct memory access comprises:

receiving a first data block from the host by the flash storage device;

storing the first data block in the flash storage device at the predetermined address;

receiving a second data block from the host by the flash storage device;

incrementing the predetermined address by the flash storage device to determine a next address; and

storing the second data block in the flash storage device at the next address.

10. A system, comprising:

a flash storage;

a memory;

an interface configured to:

receive a select signal from a host, the select signal indicating a selection between a first communication protocol and a second communication protocol, and

receive a request for a direct memory access from the host, the direct memory access corresponding to at least one of the first communication protocol or the second communication protocol based on the received select signal; and

a controller coupled to the interface, the memory and the flash storage, the controller configured to obtain a predetermined address from the memory in response to the request and transfer a plurality of data blocks in sequential addresses in the flash storage starting at the predetermined address.

11. The system of claim 10 , further comprising a memory configured to store the predetermined address, the controller further configured to read the predetermined address from the memory.

12. The system of claim 10 , wherein the flash storage comprises a storage block, the interface is further configured to receive a data block associated with the request, and the controller is further configured to erase the storage block and write the data block into the storage block.

13. The system of claim 10 , wherein the flash storage further comprises a plurality of storage blocks, the interface is further configured to receive a plurality of data blocks, and the controller is further configured to write the plurality of data blocks into the plurality of storage blocks.

14. The system of claim 13 , wherein the controller is further configured to erase the plurality of storage blocks before writing the plurality of data blocks into the plurality of storage blocks.

15. The system of claim 14 , wherein the interface is further configured to receive a signal from a first host for selecting a communication protocol for the direct memory access, and wherein the interface is further configured to receive a signal from a second host for selecting a communication protocol for transferring the plurality of data blocks.

16. The system of claim 15 , wherein the communication protocol for the direct memory access is a custom communication protocol.

17. The system of claim 15 , wherein the communication protocol for transferring the plurality of data blocks is a standard communication protocol.

18. The system of claim 15 , wherein the interface comprises an input pin for receiving the signal from the first host and the signal from the second host.

19. The system of claim 14 , wherein the interface is further configured to select a communication protocol for the direct memory access based on a first host, and wherein the interface is further configured to select a communication protocol for transferring the plurality of data blocks based on a second host.

20. The system of claim 10 , wherein the interface is further configured to receive a first data block and a second data block, and wherein the controller is further configured to store the first data block in the flash storage at the predetermined address, increment the predetermined address to identify a next address, and store the second data block in the flash storage at the next address.

21. A system comprising:

means for receiving a select signal from a host, the select signal indicating a selection between a first communication protocol and a second communication protocol;

means for receiving a request for a direct memory access from the host, the direct memory access corresponding to at least one of the first communication protocol or the second communication protocol based on the received select signal;

means for obtaining a predetermined address from a memory in a flash storage device; and

means for performing the direct memory access at sequential addresses in flash storage in the flash storage device starting at the predetermined address.

22. The system of claim 21 , wherein performing the direct memory access comprises storing a plurality of data blocks in the flash storage.

23. The system of claim 22 , further comprising means for reading the plurality of data blocks in the flash storage.

24. The system of claim 23 , wherein the first communication protocol is selected for performing the direct memory access, and the second communication protocol is selected for transferring the data blocks.

25. The system of claim 24 , wherein the first communication protocol is a custom communication protocol and the second communication protocol is a standard communication protocol.

26. The system of claim 21 , wherein performing the direct memory access comprises:

means for erasing a plurality of storage blocks in the flash storage; and

means for storing a plurality of data blocks in the plurality of storage blocks.

Assignments (13)