Non-volatile semiconductor memory storing an inverse map for rebuilding a translation table
View Patent ↗A non-volatile semiconductor memory comprising (1) a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address and (2) a volatile memory. Upon a power-up of the non-volatile semiconductor memory, a translation table is generated in the volatile memory for mapping logical addresses to physical addresses in the non-volatile memory array. The generating includes reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array. The logical address corresponds to a physical address of one of the memory segments. In response to determining that the memory segment corresponding to the logical address is valid, the translation table is updated using the logical address.
1. A non-volatile semiconductor memory comprising:
a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address;
a volatile memory; and
control circuitry operable to:
upon a power-up of the non-volatile semiconductor memory, generate, in the volatile memory, a translation table for mapping logical addresses to physical addresses in the non-volatile memory array, the control circuitry operable to generate by at least:
reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments; and
in response to determining that the memory segment corresponding to the logical address is valid, updating the translation table using the logical address.
2. The non-volatile semiconductor memory of claim 1 , wherein the control circuitry is operable to generate substantially the entire translation table by reading logical addresses from the non-volatile memory array.
3. The non-volatile semiconductor memory of claim 1 , wherein the control circuitry is further operable to maintain a chronological write order of the plurality of memory segments.
4. The non-volatile semiconductor memory of claim 3 , wherein the chronological write order is maintained in a write order table.
5. The non-volatile semiconductor memory of claim 4 , wherein the write order table is saved to the non-volatile memory array when a power failure is detected.
6. The non-volatile semiconductor memory of claim 3 , wherein the control circuitry is further operable to generate the translation table based on the chronological write order.
7. The non-volatile semiconductor memory of claim 6 , wherein the control circuitry is further operable to generate the translation table based on the chronological write order by reading logical addresses from the non-volatile memory array in the chronological write order or in a reverse order from the chronological write order.
8. The non-volatile semiconductor memory of claim 3 , wherein the control circuitry is further operable to determine whether a memory segment is invalid based on the chronological write order.
9. The non-volatile semiconductor memory of claim 1 , wherein the control circuitry is further operable to:
receive a write command from a host; and
update the translation table based on the received write command.
10. The non-volatile semiconductor memory of claim 1 , wherein a first block of the non-volatile memory array comprises the logical address of the inverse map and the corresponding memory segment.
11. The non-volatile semiconductor memory of claim 1 , wherein a first block of the non-volatile memory array comprises the logical address of the inverse map and a second block of the non-volatile memory array comprises the corresponding memory segment.
12. The non-volatile semiconductor memory of claim 1 , wherein each of the plurality of blocks comprises a plurality of memory segments with each of the plurality of memory segments assigned a physical address.
13. A method of operating a non-volatile semiconductor memory comprising (1) a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address and (2) a volatile memory, the method comprising:
upon a power-up of the non-volatile semiconductor memory, generating, in the volatile memory, a translation table for mapping logical addresses to physical addresses in the non-volatile memory array, the generating comprising:
reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array, wherein the logical address corresponds to a physical address of one of the memory segments; and
in response to determining that the memory segment corresponding to the logical address is valid, updating the translation table using the logical address.
14. The method of claim 13 , wherein substantially the entire translation table is generated by reading logical addresses from the non-volatile memory array.
15. The method of claim 13 , further comprising maintaining a chronological write order of the plurality of memory segments.
16. The method of claim 15 , wherein the chronological write order is maintained in a write order table.
17. The method of claim 16 , further comprising saving the write order table to the non-volatile memory array when a power failure is detected.
18. The method of claim 15 , wherein the generating of the translation table is based on the chronological write order.
19. The method of claim 18 , wherein the generating of the translation table is based on the chronological write order by reading logical addresses from the non-volatile memory array in the chronological write order or in a reverse order from the chronological write order.
20. The method of claim 15 , further comprising determining whether a memory segment is invalid based on the chronological write order.
21. The method of claim 13 , further comprising:
receiving a write command; and
updating the translation table based on the received write command.
22. The method of claim 13 , wherein each of the plurality of blocks comprises a plurality of memory segments with each of the plurality of memory segments assigned a physical address.