IP Library Granted Patent US 10,209,891
Granted Patent B2
US 10,209,891 · App. 14/833,817 · Granted Feb 19, 2019

Methods and systems for improving flash memory flushing

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Quick Facts
Patent No.
US 10,209,891
App. No.
14/833,817
Granted
Feb 19, 2019
Kind
B2
Abstract

Techniques for improving flash memory flushing are disclosed. In some embodiments, the techniques may be realized as a method for improving flash memory flushing including receiving a request to write to flash memory, writing data associated with the request to the flash memory, identifying a pointer to a region bitmap corresponding to a write region for the write request, marking a bit of the region bitmap corresponding to the request as dirty, and updating the pointer, using a pointer management component, to the region bitmap to contain a dirty block count.

Claims (39)

1. A method for improving flash memory flushing comprising:

receiving a request to write to flash memory;

writing data associated with the request to the flash memory;

identifying a pointer to a region bitmap corresponding to a write region for the request;

marking a bit of the region bitmap corresponding to the request as dirty; and

updating the pointer, using a pointer management component, to the region bitmap to contain a dirty block count, wherein updating the pointer to the region bitmap to contain the dirty block count comprises updating one or more higher order bits of the pointer to contain the dirty block count.

2. The method of claim 1 , wherein the pointer comprises a pointer with 48 significant lower bits and 16 higher order bits and wherein the dirty block count is stored in the 16 higher order bits.

3. The method of claim 1 , wherein marking a bit of the region bitmap corresponding to the request as dirty comprises updating the higher order bits of the pointer to contain a value of a last significant bit of the pointer, and using the updated pointer to identify the region bitmap.

4. The method of claim 1 , wherein the pointer comprises one of an array of pointers and wherein the array of pointers is ordered by a dirty block count in each of the pointers.

5. The method of claim 4 , further comprising:

identifying a dirtiest region of a plurality of regions of the flash memory using the ordered array of pointers; and

writing one or more blocks of the dirtiest region to conventional storage.

6. The method of claim 5 , wherein writing one or more blocks to conventional storage is triggered by detection of one or more factors.

7. The method of claim 6 , wherein the one or more factors comprise at least one of: a specified threshold of dirty blocks attained, a level of CPU utilization, a level of network utilization, a level of convention storage input/output, an aging out of one or more blocks from cache, and a user specified preference.

8. The method of claim 5 , wherein writing one or more blocks of the dirtiest region to conventional storage comprises using a base address of a region bitmap and an offset associated with a bit of the region bitmap to identify a logical block address associated with data to be written to conventional storage.

9. The method of claim 5 further comprising after writing one or more blocks associated with a first region, identifying a second pointer in the array of pointers associated with a second dirtiest region.

10. The method of claim 9 , wherein when one or more blocks associated with a first pointer are written to conventional storage, and an offset of the second pointer becomes a starting point of the array.

11. A non-transitory machine-readable medium comprised of a series of instructions executable on a machine, that when executed by a processor, perform a method for performing flash memory flushing comprising:

receiving a request to write to flash memory;

writing data associated with the request to the flash memory;

identifying a pointer to a region bitmap corresponding to a write region for the request;

marking a bit of the region bitmap corresponding to the request as dirty; and

updating the pointer to the region bitmap to contain a dirty block count, wherein updating the pointer to the region bitmap to contain the dirty block count comprises updating one or more higher order bits of the pointer to contain the dirty block count.

12. A system for improving flash memory flushing, the system comprising:

a storage media device;

a PCIe-based device controller associated with the storage media device, wherein the PCIe-based device controller is configured to:

receive a request to write to flash memory;

write data associated with the request to the flash memory;

identify a pointer to a region bitmap corresponding to a write region for the request;

mark a bit of the region bitmap corresponding to the request as dirty; and

update one or more higher order bits of the pointer to the region bitmap to contain a dirty block count.

13. The system of claim 12 , wherein the pointer comprises a pointer with 48 significant lower bits and 16 higher order bits and wherein the dirty block count is stored in the 16 higher order bits.

14. The system of claim 12 , wherein marking a bit of the region bitmap corresponding to the request as dirty comprises updating the higher order bits of the pointer to contain a value of a last significant bit of the pointer, and using the updated pointer to identify the region bitmap.

15. The system of claim 12 , wherein the pointer comprises one of an array of pointers and wherein the array of pointers is ordered by a dirty block count in each of the pointers.

16. The system of claim 15 , wherein the PCIe-based device controller is further configured to:

identify a dirtiest region of a plurality of regions of the flash memory using the ordered array of pointers; and

write one or more blocks of the dirtiest region to conventional storage.

17. The system of claim 16 , wherein writing one or more blocks to conventional storage is triggered by detection of one or more factors.

18. The system of claim 17 , wherein the one or more factors comprise at least one of: a specified threshold of dirty blocks attained, a level of CPU utilization, a level of network utilization, a level of convention storage input/output, an aging out of one or more blocks from cache, and a user specified preference.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2016
From: NOÉ, DANIEL PETER
To: HGST NETHERLANDS B.V.
Reel/Frame 037492/0409 →