IP Library Granted Patent US 11,636,039
Granted Patent B2
US 11,636,039 · App. 17/746,849 · Granted Apr 25, 2023

Mapping for multi-state programming of memory devices

Inventors: Bernie Rub (Sudbury, MA); Mostafa El Gamal (Worcester, MA); Niranjay Ravindran (Rochester, MN); Richard David Barndt (San Diego, CA); Henry Chin (Fremont, CA); Ravi J. Kumar (Redwood City, CA); James Fitzpatrick (Laguna Niguel, CA)
Assignee: Western Digital Technologies, Inc.
G06F12/0873G06F11/1068G06F12/0246G11C8/10G11C11/5628G06F2212/283G06F2212/403G06F2212/608G11C2211/5641
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,636,039
App. No.
17/746,849
Granted
Apr 25, 2023
Kind
B2
Abstract

Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Claims (76)

1. A method for a data storage system, the method implemented using one or more controllers, the method comprising:

generating, based on a first set of data, a first mapped data and a second mapped data based on a Gray code encoding;

writing to a first memory, in a first mode, the first mapped data;

generating a second set of data, based on the first mapped data and the second mapped data; and

writing to the first memory, in a second mode, data based on the second set of data,

wherein:

the first mapped data is representable in first rows and one or more columns;

the second mapped data is representable in second rows and at least one column;

the at least one column of the second mapped data includes more transitions than any one of the one or more columns of the first mapped data; and

each transition corresponds to a change between neighboring data.

2. The method of claim 1 , wherein the at least one column of the second mapped data includes more transitions than all of the one or more columns of the first mapped data.

3. The method of claim 1 , wherein:

generating the second set of data comprises generating the second set of data, represented by a set of balanced Gray codes, based on a combination of the first mapped data and the second mapped data; and

the set of balanced Gray codes includes a sum of transitions that is not greater than a maximum number of read levels for writing in the second mode to the first memory.

4. The method of claim 1 , wherein:

the first mode and the second mode correspond to different modes of writing to the first memory; and

generating the second set of data comprises generating the second set of data based on an inverse mapping of the first mapped data and the second mapped data.

5. The method of claim 1 , wherein:

the first mapped data comprises a first plurality of data represented by a plurality of balanced Gray codes; and

the second mapped data comprises a second plurality of data.

6. The method of claim 5 , wherein:

the plurality of balanced Gray codes include a sum of transitions for each of the one or more columns;

a total of the sums of the transitions for all of the one or more columns is not greater than a maximum number of read levels for writing in the first mode to the first memory; and

a sum of the transitions for one of the one or more columns and a sum of the transitions for a next one of the one or more columns are same or differ by not more than one.

7. The method of claim 1 , wherein:

the second set of data comprises the first set of data; and

an amount of the first mapped data is greater than an amount of the second mapped data.

8. A data storage system, comprising:

a first memory; and

one or more controllers configured to cause:

generating, based on a first set of data, a first mapped data and a second mapped data based on a Gray code encoding;

writing to the first memory, in a first mode, the first mapped data;

generating a second set of data, based on the first mapped data and the second mapped data; and

writing to the first memory, in a second mode, data based on the second set of data,

wherein:

the first mapped data is representable in first rows and one or more columns;

the second mapped data is representable in second rows and at least one column;

the at least one column of the second mapped data includes more transitions than any one of the one or more columns of the first mapped data; and

each transition corresponds to a change between neighboring data.

9. The data storage system of claim 8 , wherein the at least one column of the second mapped data includes more transitions than all of the one or more columns of the first mapped data.

10. The data storage system of claim 8 , wherein:

generating the second set of data comprises generating the second set of data, represented by a set of balanced Gray codes, based on a combination of the first mapped data and the second mapped data; and

the set of balanced Gray codes includes a sum of transitions that is not greater than a maximum number of read levels for writing in the second mode to the first memory.

11. The data storage system of claim 8 , wherein:

the first mode and the second mode correspond to different modes of writing to the first memory; and

generating the second set of data comprises generating the second set of data based on an inverse mapping of the first mapped data and the second mapped data.

12. The data storage system of claim 8 , wherein:

the first mapped data comprises a first plurality of data represented by a plurality of balanced Gray codes; and

the second mapped data comprises a second plurality of data.

13. The data storage system of claim 12 , wherein:

the plurality of balanced Gray codes include a sum of transitions for each of the one or more columns;

a total of the sums of the transitions for all of the one or more columns is not greater than a maximum number of read levels for writing in the first mode to the first memory; and

a sum of the transitions for one of the one or more columns and a sum of the transitions for a next one of the one or more columns are same or differ by not more than one.

14. The data storage system of claim 8 , wherein data in every two rows of the second mapped data are an identical pair.

15. The data storage system of claim 8 , wherein:

a number of transitions for the first mapped data comprises seven transitions; and

a number of transitions for the second mapped data comprises eight transitions.

16. The data storage system of claim 8 , wherein:

the second set of data comprises the first set of data; and

an amount of the first mapped data is greater than an amount of the second mapped data.

17. The data storage system of claim 8 , wherein the one or more controllers are configured to cause storing the second mapped data into a cache that is different from the first memory.

18. An apparatus, comprising:

a first memory;

means for generating, based on a first set of data, a first mapped data and a second mapped data based on a Gray code encoding;

means for writing to the first memory, in a first mode, the first mapped data;

means for generating a second set of data, based on the first mapped data and the second mapped data; and

means for writing to the first memory, in a second mode, data based on the second set of data,

wherein:

the first mapped data is representable in first rows and one or more columns;

the second mapped data is representable in second rows and at least one column;

the at least one column of the second mapped data includes more transitions than any one of the one or more columns of the first mapped data; and

each transition corresponds to a change between neighboring data.

19. The apparatus of claim 18 , wherein the at least one column of the second mapped data includes more transitions than all of the one or more columns of the first mapped data.

20. The apparatus of claim 18 , wherein:

the means for generating the second set of data comprises means for generating the second set of data, represented by a set of balanced Gray codes, based on a combination of the first mapped data and the second mapped data; and

the set of balanced Gray codes includes a sum of transitions that is not greater than a maximum number of read levels for writing in the second mode to the first memory.

Assignments (9)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 7TH INVENTOR'S NAME AND ATTORNY DOCKET NUMBER PREVIOUSLY RECORDED AT REEL: 060102 FRAME: 0958. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Sep 6, 2022
From: RUB, BERNIE; EL GAMAL, MOSTAFA; RAVINDRAN, NIRANJAY; BARNDT, RICHARD DAVID; CHIN, HENRY; KUMAR, RAVI J.; FITZPATRICK, JAMES
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 061622/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2022
From: RUB, BERNIE; EL GAMAL, MOSTAFA; RAVINDRAN, NIRANJAY; BARNDT, RICHARD DAVID; CHIN, HENRY; KUMAR, RAVI J.; FITZPATRICK, JIM
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060102/0958 →