Predicting host access rates for variable bit rate data streams using a data storage controller
Methods and apparatus for predicting a future estimated host read access rate for variable bit rate (VBR) data streams that include Program Clock Reference (PCR) indicators or other playback clock synchronization values. The VBR data stream may be encoded, for example, as a Motion Picture Experts Group (MPEG)-transport stream (TS). In some examples, a data storage device with a non-volatile memory (NVM) array parses an MPEG-TS VBR data stream retrieved from the NVM array to identify PCRs. Using the PCRs, the device estimates the future host data access rate for additional portions of MPEG-TS VBR data not yet requested by the host. The data storage device may then adaptively adjust background (e.g. overhead) management operations such as garbage collection based on the future host data access rate.
1. A data storage device, comprising:
a non-volatile memory (NVM); and
a data storage controller including a processor configured to:
obtain NVM read commands from a host for reading variable bit rate (VBR) data from the NVM, each NVM read command including a logical block address (LBA);
process the read commands to read and transfer the VBR data from the NVM to the host as a VBR data stream;
identify clock synchronization values within the VBR data stream;
predict a host data access rate for additional VBR data not yet requested by the host, the prediction based, in part, on the clock synchronization values and the LBAs; and
control an NVM operation based on the predicted host data access rate;
wherein the clock synchronization values are program clock references (PCRs) and there is at least one LBA associated with each PCR; and
wherein the processor is further configured to predict the host data access rate for the additional VBR data not yet requested by the host based on the LBAs associated with the PCRs using a read look ahead (RLA) component of the data storage device.
2. The data storage device of claim 1 , wherein the processor is configured to predict the host data access rate for the additional VBR data by:
determining an amount of data within the VBR stream associated with a time interval between a first PCR and a second PCR of the VBR stream with the amount of data determined, in part, using the RLA; and
estimating the host data access rate for the additional VBR data based on the amount of data and the time interval between the first PCR and the second PCR.
3. The data storage device of claim 2 , wherein the first PCR is within a first portion of the VBR data requested by the host in a first read access request received by the data storage controller and wherein the second PCR is within a second portion of the VBR data not yet requested by the host and with the amount of data associated with the second PCR determined, in part, using the RLA.
4. The data storage device of claim 1 , wherein the processor is further configured to control, based on the predicted host data access rate, one or more of: a) a read trim operation; b) an amount of memory used for RLA cache operations; c) transfer random access memory (TRAM) operations; d) a sharing or subdivision of resources for storage and computations; and e) error correction code (ECC) operations.
5. The data storage device of claim 1 , wherein the processor is further configured to control a machine learning image recognition operation based on the predicted host data rate to devote a first amount of processing resources to the image recognition operation in response to the predicted host data rate exceeding a threshold and to devote a second, different amount of processing resources to the image recognition operation in response to the predicted host data rate not exceeding the threshold.
6. The data storage device of claim 1 , wherein the processor is further configured to control a complexity level of an ECC processing flow by being configured to compare the predicted host data access rate to a threshold and select:
(a) a first ECC processing flow during intervals of time when the predicted host data access rate is below a threshold, and
(b) a second, different ECC processing flow during intervals of time when the predicted host data access rate is not below the threshold, wherein the first ECC processing flow is a more complex ECC processing flow than the second ECC processing flow.
7. The data storage device of claim 6 , wherein the processor is further configured to (a) select an ECC processing flow configured to only detect but not correct errors as the first ECC processing flow and to (b) select an ECC processing flow configured to both detect and correct errors as the second ECC processing flow.
8. The data storage device of claim 1 , wherein the processor is further configured to:
(a) decrease an amount of processing bandwidth devoted to a read scrub background operation performed by the processor, in response to the predicted host data access rate being higher than a threshold, and
(b) increase the amount of processing bandwidth devoted to the read scrub background operation, in response to the predicted host data access rate not being higher than the threshold.
9. The data storage device of claim 1 , wherein the RLA component is configured to perform speculative reads from the NVM.
10. The data storage device of claim 9 , wherein the NVM is a NAND-based NVM formed within a die and wherein the RLA component is configured to store data from the speculative reads within latches within the die.
11. A method for use with a data storage device comprising non-volatile memory (NVM), the method comprising:
obtaining read commands from a host for reading variable bit rate (VBR) data from the NVM, each NVM read command including a logical block address (LBA);
executing the read commands to read and transfer the VBR data from the NVM to the host as a VBR data stream;
identifying clock synchronization values within the VBR data stream;
predicting a host data access rate for additional VBR data not yet requested by the host, the prediction based, in part, on the clock synchronization values and the LBAs; and
controlling an NVM operation based on the predicted host data access rate;
wherein the clock synchronization values are program clock references (PCRs) and there is at least one LBA associated with each PCR; and
wherein the host data access rate for the additional VBR data not yet requested by the host is predicted based on the LBAs associated with the PCRs using a read look ahead (RLA) component of the data storage device.
12. The method of claim 11 , further comprising predicting the host data access rate for the additional VBR data by:
determining an amount of data within the VBR data stream associated with a time interval between a first PCR and a second PCR of the VBR stream with the amount of data determined, in part, using the RLA; and
estimating a future host data access rate for the additional VBR data based on the amount of data and the time interval between the first PCR and the second PCR.
13. The method of claim 12 , wherein the first PCR is within a first portion of the VBR data requested by the host in a first read access request received by the data storage device and wherein the second PCR is within a second portion of the VBR data not yet requested by the host and with the amount of data associated with the second PCR determined, in part, using the RLA.
14. The method of claim 11 , further comprising controlling, based on the predicted host data access rate, one or more of: a) a read trim operation; b) an amount of memory used for RLA cache operations; c) transfer random access memory (TRAM) operations; d) a sharing or subdivision of resources for storage and computations; and e) error correction code (ECC) operations.
15. The method of claim 14 , further comprising controlling a complexity level of an ECC processing flow by comparing the predicted host data access rate to a threshold and (a) selecting a first ECC processing flow during intervals of time when the predicted host data access rate is below the threshold and (b) selecting a second different ECC processing flow during intervals of time when the predicted host data access rate is not below the threshold, wherein the first ECC processing flow is a more complex ECC processing flow than the second ECC processing flow.
16. The method of 15 , further comprising (a) selecting an ECC processing flow configured to only detect but not correct errors as the first ECC processing flow and (b) selecting an ECC processing flow configured to both detect and correct errors as the second ECC processing flow.
17. The method of claim 11 , further comprising controlling a machine learning image recognition operation based on the predicted host data rate by devoting a first amount of processing resources to the image recognition operation in response to the predicted host data rate exceeding a threshold and by devoting a second, different amount of processing resources to the image recognition operation in response to the predicted host data rate not exceeding the threshold.
18. The method of claim 11 , further comprising:
(a) decreasing an amount of processing bandwidth devoted to a read scrub background operation performed by the data storage device, in response to the predicted host data access rate being higher than a threshold and
(b) increasing the amount of processing bandwidth devoted to the read scrub background operation in response to the predicted host data access rate not being higher than the threshold.
19. The method of claim 11 , further comprising performing speculative reads from the NVM using the RLA component.
20. The method of claim 19 , wherein the NVM is a NAND-based NVM formed within a die and wherein the method further comprises storing data from the speculative reads within latches within the die.
21. An apparatus for use with a non-volatile memory (NVM), the apparatus comprising:
means for obtaining read commands from a host for reading variable bit rate (VBR) data from the NVM, each NVM read command including a logical block address (LBA);
means for reading the VBR data from the NVM;
means for transferring the VBR data from the NVM to the host as a VBR data stream;
means for identifying playback clock values within the VBR data stream;
means for predicting a host data access rate for additional VBR data not yet requested by the host based, in part, on the playback clock values and the LBAs; and
means for controlling an NVM operation based on the predicted host data access rate;
wherein the playback clock values are program clock references (PCRs) and there is at least one LBA associated with each PCR; and
wherein the means for predicting the host data access rate comprises means for predicting the host data access rate based on the LBAs associated with the PCRs using a read look ahead (RLA) component of the apparatus.
22. The apparatus of claim 21 , further comprising means for performing speculative reads from the NVM using the RLA component.