Granted Patent B2

US 10,733,122 · App. 16/554,519 · Granted Aug 4, 2020

Inventors: Mark Moshayedi (Newport Coast, CA); Seyed Jalal Sadr (Irvine, CA)

Assignee: Western Digital Technologies, Inc.

G06F13/28G06F3/0611G06F3/0659G06F3/0679G06F12/0246G06F13/102G06F13/1668G06F13/4068G06F13/42G06F2212/7202

Abstract

Claims (60)

1. A computer-implemented method, comprising:

receiving a select signal from a host, the select signal indicating selection of a first communication protocol or a second communication protocol different from the first communication protocol;

when a request signal, indicating a request for a direct memory access operation, is received from the host, sending a ready signal to the host based on the request for the direct memory access operation;

when the select signal indicates using the first communication protocol, performing the direct memory access operation for transferring data between the host and a storage device using the first communication protocol, wherein one or more controllers perform the direct memory access operation subsequent to sending the ready signal; and

when the select signal indicates using the second communication protocol, transferring data between the host and the storage device using the second communication protocol.

2. The computer-implemented method of claim 1 , further comprising:

receiving a response signal, the response signal indicating readiness to transfer data for the request;

sending the ready signal to the host based on the received response signal; and

receiving an acknowledgement signal from the host based on the ready signal, wherein the direct memory access operation is performed subsequent to receiving the acknowledgement signal.

3. The computer-implemented method of claim 1 , further comprising:

obtaining at least one predetermined address from a plurality of predetermined addresses stored in a memory;

determining whether the direct memory access operation is a read or write operation;

transferring the data from the storage device at sequential addresses starting at, at least one predetermined address when the direct memory access operation is a read operation; and

transferring the data to the storage device at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a write operation.

4. The computer-implemented method of claim 1 , wherein the request signal is processed by a first protocol controller when the select signal indicates the first communication protocol.

5. The computer-implemented method of claim 1 , wherein the request signal is processed by a second protocol controller when the select signal indicates the second communication protocol.

6. A data storage system, comprising:

a storage device; and

one or more controllers configured to cause:

receiving a select signal from a host, the select signal indicating selection of a first communication protocol or a second communication protocol different from the first communication protocol;

when a request signal, indicating a request for a direct memory access operation, is received from the host, sending a ready signal to the host based on the request for the direct memory access operation;

when the select signal indicates using the first communication protocol, performing the direct memory access operation for transferring data between the host and the storage device, using the first communication protocol, wherein the one or more controllers are configured to perform the direct memory access operation subsequent to sending the ready signal; and

when the select signal indicates using the second communication protocol, transferring data between the host and the storage device, using the second communication protocol.

7. The data storage system of claim 6 , wherein the one or more controllers comprise an interface and a controller, and wherein the interface is configured to:

process requests between the host and the storage device, the interface comprising a first protocol controller associated with the first communication protocol and a second protocol controller associated with the second communication protocol, wherein the controller is coupled to the storage device and the interface.

8. The data storage system of claim 6 , wherein the one or more controllers comprise an interface and a controller, and wherein the interface is configured to cause:

receiving a response signal from the controller, the response signal indicating that the controller is ready to transfer data for the request;

sending the ready signal to the host based on the received response signal; and

receiving an acknowledgement signal from the host based on the ready signal, wherein the controller is configured to perform the direct memory access operation subsequent to receiving the acknowledgement signal.

9. The data storage system of claim 6 , wherein the one or more controllers comprise a controller, and wherein the controller is configured to perform the direct memory access operation at a starting predetermined address in the storage device independent of the host providing an address of the storage device for the direct memory access operation.

10. The data storage system of claim 6 , wherein the one or more controllers comprise a controller, and a memory coupled to the controller, the memory is configured to store a plurality of predetermined addresses of the storage device, wherein the controller is configured to cause:

obtaining at least one predetermined address from the plurality of predetermined addresses stored in the memory;

determining whether the direct memory access operation is a read or write operation;

transferring the data from the storage device at sequential addresses starting at, at least one predetermined address when the direct memory access operation is a read operation; and

transferring the data to the storage device at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a write operation.

11. The data storage system of claim 7 , wherein the request signal is processed by the first protocol controller when the select signal indicates the first communication protocol.

12. The data storage system of claim 7 , wherein the request signal is processed by the second protocol controller when the select signal indicates the second communication protocol.

13. The data storage system of claim 6 , wherein the one or more controllers are configured to write the data into the storage device in the direct memory access operation when the select signal indicates the first communication protocol.

14. The data storage system of claim 13 , wherein the one or more controllers comprise an interface and a controller, wherein the interface is configured to cause:

receiving a write signal over a control bus to the host;

receiving, subsequent to receiving the write signal, a first data block of a sequence of data blocks from the host, the write signal being asserted at a start of the first data block; and

providing the first data block to the controller, the write signal being deasserted by the host according to the first communication protocol.

15. The data storage system of claim 14 , wherein the first communication protocol specifies a minimum time between assertion and deassertion of the write signal.

16. The data storage system of claim 6 , wherein the one or more controllers comprise an interface and a controller, wherein the controller is configured to cause:

reading the data from the storage device in the direct memory access operation when the select signal indicates the second communication protocol.

17. The data storage system of claim 16 , wherein the one or more controllers comprise an interface and a controller, wherein the interface is configured to cause:

receiving a first data block of a sequence of data blocks;

asserting a read signal over a control bus to the host;

sending the first data block to the host, the read signal being asserted at start of the first data block; and

deasserting the read signal according to the second communication protocol.

18. The data storage system of claim 17 , wherein the second communication protocol specifies a minimum time between assertion and deassertion of the read signal.

19. A data storage system, comprising:

means for receiving a select signal from a host, the select signal indicating selection of a first communication protocol or a second communication protocol different from the first communication protocol;

when a request signal, indicating a request for a direct memory access operation, is received from the host, means for sending a ready signal to the host based on the request for the direct memory access operation;

when the select signal indicates using the first communication protocol, means for performing the direct memory access operation for transferring data between the host and a storage device using the first communication protocol, wherein the means for performing the direct memory access operation is configured to perform the direct memory access operation subsequent to sending the ready signal; and

when the select signal indicates using the second communication protocol, means for transferring data between the host and the storage device using the second communication protocol.

20. The data storage system of claim 19 , comprising

means for receiving a response signal indicating readiness to transfer data for the request;

means for sending the ready signal to the host based on the received response signal; and

means for receiving an acknowledgement signal from the host based on the ready signal, wherein the means for performing the direct memory access operation is configured to perform the direct memory access operation subsequent to receiving the acknowledgement signal.

Assignments (13)