Error detection for training non-volatile memories
The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.
1. A non-volatile memory (NVM) controller, comprising:
a host interface for communicating with a host device;
a memory interface for communicating with a NVM via one or more channels;
a cyclic redundancy check (CRC) circuit configured to generate a CRC code; and
a calibration circuit configured to provide re-training data to the NVM,
wherein the NVM controller is configured to:
(i) receive a CRC code from the NVM via the memory interface,
(ii) compare the received CRC code with the generated CRC code to detect error,
(iii) determine if a re-training condition has been met, based on the comparison of the received CRC code with the generated CRC code, and
(iv) activate the calibration circuit, if the re-training condition has been met, to re-train the NVM using the re-training data.
2. The NVM controller of claim 1 , wherein the NVM comprises a NAND memory, and the NVM controller is configured to receive the CRC code in response to a read command.
3. The NVM controller of claim 1 , wherein the NVM controller is further configured to:
determine if a CRC condition is present, and
receive CRC code from the NVM only if the CRC condition is present.
4. The NVM controller of claim 3 , wherein the CRC condition comprises at least one of (i) expiration of a predetermined period of time, (ii) a predetermined number of read errors detected, and/or (iii) a temperature delta detected.
5. The NVM controller of claim 1 , wherein the re-training condition comprises at least one of:
a predetermined number of CRC errors detected within a predetermined time period, and/or
a predetermined number of CRC errors detected after a temperature delta threshold has been met or exceeded.
6. The NVM controller of claim 1 , wherein the generated and received CRC codes each comprise one of (i) a fixed-length binary sequence or (ii) a data pattern.
7. The NVM controller of claim 1 , wherein the calibration circuit is configured to calibrate the NVM by matching impedance between the NVM controller and the NVM.
8. The NVM controller of claim 1 , wherein the calibration circuit is configured to calibrate the NVM based on a duty cycle of a strobe of the controller.
9. The NVM controller of claim 1 , wherein the calibration circuit is configured to calibrate the NVM by correcting at least one of a strobe and a phase relationship between data and the strobe, wherein the strobe and the data are provided via the memory interface to the NVM.
10. A non-volatile memory (NVM) controller, configured to communicate with a host and a NVM, comprising:
a processing circuit configured to determine (i) a cyclic redundancy check (CRC) condition indicative of error in the NVM, and (ii) if a re-training condition, based on the CRC condition, has been met;
a CRC circuit operatively coupled to the processing circuit and configured to generate a CRC code when the CRC condition is met, wherein the processing circuit is configured to compare a CRC code received from the NVM controller with the generated CRC code to detect error; and
a calibration circuit operatively coupled to the processing circuit and configured to re-train the NVM if the processing circuit detects error and the re-training condition has been met.
11. The NVM controller of claim 10 , wherein the NVM comprises a NAND memory, and the NVM controller is configured to receive the CRC code in response to a read command.
12. The NVM controller of claim 10 , wherein the CRC condition comprises at least one of (i) expiration of a predetermined period of time, (ii) a predetermined number of read errors detected, and/or (iii) a temperature delta detected.
13. The NVM controller of claim 10 , wherein the re-training condition comprises at least one of:
a predetermined number of CRC errors detected within a predetermined time period, and/or
a predetermined number of CRC errors detected after a temperature delta threshold has been met or exceeded.
14. The NVM controller of claim 10 , wherein the generated and received CRC codes each comprise one of (i) a fixed-length binary sequence or (ii) a data pattern.
15. The NVM controller of claim 10 , wherein the calibration circuit is configured to calibrate the NVM by matching impedance between the NVM controller and the NVM.
16. The NVM controller of claim 10 , wherein the calibration circuit is configured to to calibrate the NVM based on a duty cycle of a strobe of the controller.
17. The NVM controller of claim 10 , wherein the calibration circuit is configured to calibrate the NVM by correcting at least one of a strobe and a phase relationship between data and the strobe, wherein the strobe and the data are provided via the memory interface to the NVM.
18. A method of operating a non-volatile memory (NVM) controller, configured to communicate with a host and a NVM, comprising:
determining a cyclic redundancy check (CRC) condition for detecting error in the NVM;
generating a CRC code comprising a fixed-length binary sequence when the CRC condition is determined;
receiving a fixed-length binary sequence CRC code from the NVM in response to a read command from the NVM controller;
comparing the CRC code received from the NVM with the generated CRC code to detect error;
determining if a re-training condition has been met based on detected error in the comparing of the CRC code; and
re-training the NVM if the comparison of the CRC codes is indicative of error and the re-training condition has been met.
19. The method of claim 18 , wherein the CRC condition comprises at least one of (i) expiration of a predetermined period of time, and/or (ii) a temperature delta detected.
20. The method of claim 18 , wherein the re-training condition comprises at least one of:
a predetermined number of CRC errors detected within a predetermined time period, and/or
a predetermined number of CRC errors detected after a temperature delta threshold has been met or exceeded.
21. The method of claim 18 , wherein re-training the NVM comprises calibrating the NVM by matching impedance between the NVM controller and the NVM.
22. The method of claim 21 , wherein re-training the NVM comprises calibrating the NVM based on re-training data received from the NVM and correcting at least one of timing and phase of the re-training data received from the NVM.
23. A non-volatile memory (NVM) controller, configured to communicate with a host and a NVM, comprising:
means for determining a cyclic redundancy check (CRC) condition for detecting error in the NVM;
means for generating a CRC code when the CRC condition is determined;
means for comparing a CRC code received from the NVM controller with the generated CRC code to detect error;
means for determining if a re-training condition has been met, based on detected error in the comparing of the CRC code; and
means for re-training the NVM if the means for comparing CRC code detects error and the re-training condition has been met.