Separate storage and control of static and dynamic neural network data within a non-volatile memory array
Methods and apparatus are disclosed for managing the storage of static and dynamic neural network data within a non-volatile memory (NVM) die for use with deep neural networks (DNN). Some aspects relate to separate trim sets for separately configuring a static data NVM array for static input data and a dynamic data NVM array for dynamic synaptic weight data. For example, the static data NVM array may be configured via one trim set for data retention, whereas the dynamic data NVM array may be configured via another trim set for write performance. The trim sets may specify different configurations for error correction coding, write verification, and read threshold calibration, as well as different read/write voltage thresholds. In some examples, neural network regularization is provided within a DNN by setting trim parameters to encourage bit flips to avoid overfitting. Some examples relate to managing non-DNN data, such as stochastic gradient data.
1. A memory die, comprising:
non-volatile memory (NVM) elements; and
processing circuitry configured to:
store a first set of data for a multidimensional computation procedure in a first set of the NVM elements using a first set of NVM access parameters selected for use with the first set of data;
generate a second set of data from the first set of data using the multidimensional computation procedure, wherein the second set of data has a rate of change that is greater than a rate of change of the first set of data; and
store the second set of data in a second set of the NVM elements using a second set of NVM access parameters selected for use with the second set of data.
2. The memory die of claim 1 , wherein the multidimensional computation procedure comprises a neural network backpropagation procedure, the first set of data comprises a first set of neural network data, the second set of data comprises a second set of neural network data, and the processing circuitry is further configured to generate the second set of neural network data from the first set of neural network data using the neural network backpropagation procedure.
3. The memory die of claim 1 , wherein the first set of NVM access parameters comprise parameters for controlling read and write access to the first set of NVM elements, and the second set of NVM access parameters comprise parameters for controlling read and write access to the second set of NVM elements, and the processing circuitry is further configured to:
initialize the first set of NVM elements using the first set of NVM access parameters prior to storing the first set of data in the first set of NVM elements; and
initialize the second set of NVM elements using the second set of NVM access parameters prior to storing the second set of data in the second set of NVM elements.
4. The memory die of claim 1 , wherein the first and second sets of NVM access parameters comprise one or more of: a program voltage setting, a program pulse width, a read threshold, a program threshold, an error correction control parameter, a write verification control parameter, and a read threshold calibration control parameter, and wherein the processing circuitry is further configured to adjust at least one of the first and second sets of NVM access parameters following storage of the first set of data.
5. The memory die of claim 1 , wherein initial values of the first and second sets of NVM access parameters are stored in a boot memory of the memory die and wherein the processing circuitry is further configured to read the initial values from the boot memory.
6. The memory die of claim 1 , wherein the processing circuitry is further configured to adjust the first set of NVM access parameters to provide longer data retention as compared to a duration of data retention provided using the second set of NVM access parameters.
7. The memory die of claim 1 , wherein the processing circuitry is further configured to adjust the second set of NVM access parameters to provide faster write speeds as compared to write speeds provided using the first set of NVM access parameters.
8. The memory die of claim 1 , wherein the first and second sets of NVM access parameters comprise error correction control parameters, and wherein the processing circuitry is further configured, by the error correction control parameters, to (a) disable error correction or (b) use fewer error correction bits as compared to a number of error correction bits used by the processing circuitry for storing data not involved in the multidimensional computation procedure.
9. The memory die of claim 1 , wherein the first and second sets of NVM access parameters comprise write verification control parameters, and wherein the processing circuitry is further configured, by the write verification control parameters, to perform one or more of (a) provide write verification for the storage of the first set of data, (b) disable write verification for the storage of the second set of data or (c) use fewer write verification pulses for the storage of the second set of data as compared to a number of pulses involved in write verification of the first set of data.
10. The memory die of claim 1 , wherein the processing circuitry is further configured to regularize a neural network represented by data stored in the first and second sets of NVM elements by setting one or more of the first and second sets of NVM access parameters to cause at least a threshold number of bit flips within data stored in one or more of the first and second sets of NVM elements.
11. A method for use with a memory die including non-volatile memory (NVM) elements, the method comprising:
storing a first set of data for a multidimensional computation procedure in a first set of NVM elements using a first set of trim parameters selected for use with the first set of data;
generating a second set of data from the first set of data using the multidimensional computation procedure, wherein the second set of data has a rate of change that is greater than a rate of change of the first set of data; and
storing the second set of data in a second set of NVM elements using a second set of trim parameters selected for use with the second set of data.
12. The method of claim 11 , wherein the multidimensional computation procedure comprises a neural network backpropagation procedure, the first set of data comprises a first set of neural network data, and the second set of data comprises a second set of neural network data, and wherein the second set of neural network data has a rate of change within the neural network backpropagation procedure that is greater than a rate of change of the first set of neural network data within the neural network backpropagation procedure.
13. The method of claim 11 , wherein the first set of trim parameters comprise trim parameters for configuring read and write access to the first set of NVM elements, and the second set of trim parameters comprise trim parameters for configuring read and write access to the second set of NVM elements.
14. The method of claim 13 , wherein the first and second sets of data trim parameters include one or more of: a program voltage setting, a program pulse width, a read threshold, a program threshold, an error correction control parameter, a write verification control parameter, and a read threshold calibration control parameter.
15. The method of claim 11 , further comprising adjusting the first set of trim parameters to provide greater data retention as compared to a level of data retention provided using the second set of trim parameters.
16. The method of claim 11 , further comprising adjusting the second set of trim parameters to provide greater write performance as compared to a level of write performance provided using the first set of trim parameters.
17. The method of claim 11 , wherein the first and second sets of trim parameters include parameters for controlling read threshold calibration and wherein a frequency of read threshold calibration is set differently for the first and second sets of NVM elements.
18. The method of claim 11 , further comprising setting one or more of the first and second sets of trim parameters to provide a selected bit error rate (BER) within data stored in one or more of the first and second sets of NVM elements.
19. The method of claim 11 , further comprising storing user data in a third set of NVM elements using a third set of trim parameters, wherein the first, second, and third sets of NVM access parameters are different from one another.
20. The method of claim 11 , wherein the first and second sets of NVM access parameters are different from one another.
21. The method of claim 11 , wherein the first set of data comprises static data that does not change during the multidimensional computation procedure and the second set of data comprises dynamic data that changes during the multidimensional computation procedure.
22. The method of claim 11 , wherein the first set of data comprises data that changes slower than a first threshold rate during the multidimensional computation procedure and the second set of data comprises data that changes faster than a second threshold rate during the multidimensional computation procedure.