IP Library Granted Patent US 11,775,425
Granted Patent B2
US 11,775,425 · App. 17/830,528 · Granted Oct 3, 2023

Storage system and method for enabling a software-defined dynamic storage response

Inventor: Ramanathan Muthiah (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G06F3/0611G06F3/0644G06F3/0679G06F9/30047G06F11/3037G06F12/0292G06F12/0815G11C11/4085G06F2212/7201
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Quick Facts
Patent No.
US 11,775,425
App. No.
17/830,528
Granted
Oct 3, 2023
Kind
B2
Abstract

A storage system and method for enabling a software-defined dynamic storage response are provided. In one embodiment, a controller of a storage system is configured to receive an expected response time from a host; in response to receiving the expected response time from the host, cache a logical-to-physical address table entry of a wordline; and store the cached logical-to-physical address table entry of the wordline as metadata in a next wordline along with host data. Other embodiments are provided.

Claims (40)

1. A method comprising:

performing the following in a host in communication with a plurality of pools of storage systems:

establishing a response time for each pool of storage systems, wherein each pool is associated with a different response time;

determining a host responsiveness requirement;

determining which pool of the plurality of pools of storage systems has a response time capable of meeting the host responsiveness requirement; and

sending host data and the host responsiveness requirement to the determined pool;

wherein a storage system in the determined pool is configured to store a cached logical-to-physical address table entry of a wordline in its memory as metadata in a next wordline along with the host data.

2. The method of claim 1 , further comprising requesting that each storage system in the plurality of pools provide its response time to the host.

3. The method of claim 1 , further comprising requesting that the storage system change its response time.

4. The method of claim 1 , further comprising requesting that the storage system change its flush frequency to ensure that the host responsiveness requirement is met.

5. The method of claim 4 , wherein the flush frequency relates to an initialization overhead flush.

6. The method of claim 4 , wherein the flush frequency relates to a master table flush.

7. The method of claim 4 , wherein the flush frequency relates to built parity flush.

8. The method of claim 4 , wherein the flush frequency relates to a memory block type.

9. The method of claim 4 , wherein the flush frequency relates to a number of open memory blocks.

10. The method of claim 4 , wherein the flush frequency relates to a health of a memory block.

11. A host comprising:

a memory; and

a processor configured to communicate with the memory and further configured to:

communicate with a plurality of pools of storage systems;

establish a response time for each pool of storage systems, wherein each pool is associated with a different response time;

determine a host responsiveness requirement;

determine which pool of the plurality of pools of storage systems has a response time capable of meeting the host responsiveness requirement; and

send host data and the host responsiveness requirement to the determined pool;

wherein a storage system in the determined pool is configured to store a cached logical-to-physical address table entry of a wordline in its memory as metadata in a next wordline along with the host data.

12. The host of claim 11 , wherein the processor is further configured to request that each storage system in the plurality of pools provide its response time to the host.

13. The host of claim 11 , wherein the processor is further configured to request that the storage system change its response time.

14. The host of claim 11 , wherein the processor is further configured to request that the storage system change its flush frequency to ensure that the host responsiveness requirement is met.

15. The host of claim 14 , wherein the flush frequency relates to an initialization overhead flush.

16. The host of claim 14 , wherein the flush frequency relates to a master table flush.

17. The host of claim 14 , wherein the flush frequency relates to a built parity flush.

18. The host of claim 14 , wherein the flush frequency relates to a memory block type.

19. The host of claim 14 , wherein the flush frequency relates to a number of open memory blocks or a health of a memory block.

20. A host comprising:

means for communicating with a plurality of pools of storage systems;

means for establishing a response time for each pool of storage systems, wherein each pool is associated with a different response time;

means for determining a host responsiveness requirement;

means for determining which pool of the plurality of pools of storage systems has a response time capable of meeting the host responsiveness requirement; and

means for sending host data and the host responsiveness requirement to the determined pool;

wherein a storage system in the determined pool is configured to store a cached logical-to-physical address table entry of a wordline in its memory as metadata in a next wordline along with the host data.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: MUTHIAH, RAMANATHAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060080/0590 →