NONVOLATILE MEMORY WITH FAST PROGRAM VOLTAGE RAMP DOWN

1 . An apparatus comprising:

one or more control circuits configured to connect to a plurality of nonvolatile memory cells, wherein the one or more control circuits are configured to:

program the plurality of nonvolatile memory cells by applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, one or more of the plurality of program pulses ending in a fast ramp-down from the corresponding program voltage to an offset target voltage that is offset from a post-pulse voltage by a negative kick voltage.

2 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to selectively apply the fast ramp-down such that one or more of the plurality of program pulses ends in a ramp-down from the corresponding program voltage with the post-pulse voltage as a target voltage.

3 . The apparatus of claim 2 , wherein the one or more control circuits are further configured to selectively apply the fast ramp-down only to program pulses having a corresponding program voltage above a predetermined voltage.

4 . The apparatus of claim 3 , wherein the one or more control circuits are further configured to adjust the magnitude of the negative kick voltage according to the corresponding program voltage above the predetermined voltage such that the magnitude of the negative kick voltage increases with increasing program voltage.

5 . The apparatus of claim 3 , wherein the plurality of corresponding program voltages range up to 20 volts and the predetermined voltage is between 18.5 volts and 19.5 volts.

6 . The apparatus of claim 3 , wherein the one or more control circuits are further configured to initiate ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from initiation of the fast ramp-down by a delay time.

7 . The apparatus of claim 6 , wherein the one or more control circuits are further configured to selectively extend the delay time according to the corresponding program voltage.

8 . The apparatus of claim 7 , wherein the one or more control circuits are further configured to extend the delay time according to the corresponding program voltage such that delay time increases with increasing program voltage above a predetermined voltage.

9 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to apply the plurality of program pulses at the plurality of corresponding program voltages in order of increasing program voltage and to apply the fast ramp-down to only program pulses from a predetermined pulse.

10 . The apparatus of claim 9 , wherein the one or more control circuits are further configured to increase the magnitude of the negative kick voltage from a first magnitude for the predetermined pulse to a last magnitude for a last pulse of the plurality of program pulses.

11 . The apparatus of claim 10 , wherein the one or more control circuits are further configured to initiate ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from initiation of the fast ramp-down by a delay time and to extend the delay time for later pulses of the plurality of program pulses.

12 . A method of programming a plurality of nonvolatile memory cells, comprising:

applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, each program pulse ending in a ramp-down from the corresponding program voltage; and

for one or more of the plurality of program pulses, ramping-down from the corresponding program voltage to a target voltage that is offset from a post-pulse voltage by a negative kick voltage.

13 . The method of claim 12 , further comprising:

for one or more additional program pulses of the plurality of program pulses, ramping-down from the corresponding program voltage with the post-pulse voltage as a target voltage.

14 . The method of claim 13 , further comprising:

applying the plurality of program pulses in order of increasing program voltage, the one or more of the plurality of program pulses including final pulses of the plurality of program pulses and the one or more additional program pulses including initial pulses of the plurality of program pulses.

15 . The method of claim 14 , further comprising:

increasing the magnitude of the negative kick voltage for the one or more of the plurality of program pulses according to corresponding program voltage.

16 . The method of claim 12 , further comprising:

initiating fast ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from initiation of the fast ramp-down by a delay time; and

extending the delay time for program pulses having a corresponding program voltage above a predetermined voltage.

17 . The method of claim 16 , further comprising:

extending the delay time by a variable amount such that delay time increases with increasing program voltage.

18 . A storage system comprising:

a plurality of nonvolatile memory cells arranged in NAND strings; and

means for programming the plurality of nonvolatile memory cells by applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, a first subset of the plurality of program pulses ending in a ramp-down from the corresponding program voltage to a post-pulse voltage and a second subset of the plurality of program pulses ending in a fast ramp-down from the corresponding program voltage to an offset target voltage that is offset from a post-pulse voltage by a negative kick voltage.

19 . The storage system of claim 18 wherein:

the plurality of nonvolatile memory cells are located in a memory die;

the means for programming is located in a control die; and

the memory die is bonded to the control die to form an integrated memory assembly.

20 . The storage system of claim 18 , wherein the plurality of nonvolatile memory cells are arranged in a 3D NAND structure that includes a plurality of vertical NAND strings.