Block erase schemes for cross-point non-volatile memory devices
A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.
1. A method comprising:
receiving, by a non-volatile memory device, a set of operations for executing on a group of memory cells of the non-volatile memory device;
determining, by the non-volatile memory device, from the group of memory cells a maximum block size for programming in parallel based at least upon current density and voltage drop in the group of memory cells;
defining, by the non-volatile memory device, blocks from the group of memory cells that are smaller than the maximum block size; and
executing, by the non-volatile memory device, a subset of the set of operations in parallel on each of the blocks of the group of memory cells.
2. The method of claim 1 , further comprising determining, by the non-volatile memory device, a number of iterations needed to execute the set of operations on the group of memory cells based on a block size of the blocks, wherein the block size of each of the blocks is same.
3. The method of claim 2 , further comprising:
initializing, by the non-volatile memory device, a counter with a value of one;
incrementing, by the non-volatile memory device, the counter by one upon completing execution of each of the subset of the set of operations; and
determining, by the non-volatile memory device, that the execution of the set of operations is complete upon the value of the counter exceeding the number of iterations.
4. The method of claim 1 , further comprising:
executing, by the non-volatile memory device, a first subset of the set of operations in parallel on a first block; and
executing, by the non-volatile memory device, a second subset of the set of operations on a second block upon completing execution of the first subset of the set of operations.
5. The method of claim 1 , wherein each of the blocks comprises a first subset of memory cells and a second subset of memory cells interleaved with the first subset of memory cells, and wherein the subset of the set of operations are executed on the first subset of memory cells and not on the second subset of memory cells.
6. The method of claim 1 , wherein memory cells in each of the blocks share a bit line or a word line.
7. The method of claim 1 , wherein the set of operations comprises erase operations for erasing data from the group of memory cells or program operations for writing the data to the group of memory cells.
8. The method of claim 1 , further comprising determining, by the non-volatile memory device, that the subsets of the set of operations are to be executed in parallel before determining the maximum block size.
9. The method of claim 1 , further comprising determining, by the non-volatile memory device, that the set of operations is to be executed on the group of memory cells.
10. A method comprising:
receiving, by a non-volatile memory device, a set of operations for executing on the non-volatile memory device, wherein the non-volatile memory device comprises a plurality of tiles and each of the plurality of tiles comprises a plurality of memory cells;
determining, by the non-volatile memory device, that the set of operations is to be executed on the plurality of memory cells of a first tile and a second tile of the plurality of tiles;
dividing, by the non-volatile memory device, the plurality of memory cells of each of the first tile and the second tile into a plurality of blocks, wherein each of the plurality of blocks comprises a first subset of memory cells and a second subset of memory cells interleaved with the first subset of memory cells; and
executing, by the non-volatile memory device, a first subset of the set of the operations on the first subset of memory cells of a first block of the first tile and the second tile in parallel.
11. The method of claim 10 , wherein the first subset of the set of operations are not executed on the second subset of memory cells of the first block when the first subset of the set of operations are executed on the first subset of memory cells of the first block.
12. The method of claim 10 , wherein each of the plurality of blocks comprises a same number of the plurality of memory cells.
13. The method of claim 10 , wherein a block size of each of the plurality of blocks is based upon a type of operation in the set of operations.
14. The method of claim 10 , further comprising:
determining, by the non-volatile memory device, that the execution of the first subset of the set of operations is complete; and
executing, by the non-volatile memory device, a second subset of the set of operations on a second block of the first tile and the second tile in parallel, wherein the second block includes at least some of the second subset of memory cells of the first block.
15. A data storage device comprising:
a non-volatile memory device comprising:
a memory array; and
a control module configured to
determine that a subset of operations is to be executed in parallel on a group of memory cells of the memory array; and
execute the subset of operations on a first subset of the group of memory cells in parallel without executing the subset of operations on a second subset of the group of memory cells,
wherein the second subset comprises memory cells that separate at least some adjacent pairs of memory cells in the first subset.
16. The data storage device of claim 15 , wherein the adjacent pairs of memory cells in the first subset share either a bit line or a word line.
17. The data storage device of claim 15 , wherein the non-volatile memory device is a phase change memory or a resistive random access memory.
18. The data storage device of claim 15 , wherein the group of memory cells is part of a single tile, wherein the memory array comprises a plurality of tiles and each of the plurality of tiles comprises a plurality of memory cells.
19. The data storage device of claim 15 , wherein the group of memory cells is divided between a first tile and a second tile, wherein the memory array comprises a plurality of tiles and each of the plurality of tiles comprises a plurality of memory cells.
20. An apparatus comprising:
means for receiving a set of operations for executing on a group of memory cells of a non-volatile memory device;
means for determining from the group of memory cells a maximum block size for programming in parallel based at least upon current density and voltage drop in the group of memory cells;
means for defining blocks from the group of memory cells that are smaller than the maximum block size; and
means for executing a subset of the set of operations in parallel on each of the blocks of the group of memory cells.