IP Library Granted Patent US 12,205,252
Granted Patent B2
US 12,205,252 · App. 17/847,101 · Granted Jan 21, 2025

Non-volatile memory die with bit-flip object insertion

Inventors: Daniel Joseph Linnen (Naperville, IL); Ramanathan Muthiah (Bangalore, IN); Kirubakaran Periyannan (Saratoga, CA); Nikita Thacker (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06T5/50G06T7/194G06T7/90
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,205,252
App. No.
17/847,101
Granted
Jan 21, 2025
Kind
B2
Abstract

Bit-flip object insertion techniques are provided for use with a non-volatile memory (NVM) wherein an object is inserted into a background image by flipping or inverting one or more bits within the pixels of the background image that correspond to the shape and insertion location of an object being inserted. In an illustrative example, pixels within the background image that correspond to the shape and insertion location of the object are XORed with binary 1s. This flips the bits of those pixels to change the color (hue) and/or intensity (brightness) of the pixels so the object appears in the background image. In other examples, only the most significant bits of pixels in the background image are inverted (flipped). Exemplary latch-based procedures are described herein for high-speed processing on an NVM die. Multiple plane NVM die implementations are also described for massive processing.

Claims (36)

1. A device, comprising:

a non-volatile memory (NVM) array formed on a die and configured to store a first image; and

processing circuitry formed on the die and configured to:

obtain a second image corresponding to an object to be inserted into the first image,

identify pixels within a target area of the first image for the object to be inserted, and

insert the object into the first image by inverting at least one bit within each of the identified pixels of the first image.

2. The device of claim 1 , wherein the processing circuitry is configured to invert all bits within each of the identified pixels of the first image.

3. The device of claim 2 , wherein the processing circuitry is configured to invert all bits within each of the identified pixels by XORing the identified pixels with binary 1s.

4. The device of claim 1 , wherein the processing circuitry is configured to invert only a most significant bit (MSB) within each of the identified pixels.

5. The device of claim 1 , wherein the processing circuitry is further configured to randomly determine the target area within the first image for insertion of the object.

6. The device of claim 1 , wherein the processing circuitry is further configured to obtain the target area of the first image from a data storage controller.

7. The device of claim 1 , wherein the processing circuitry is further configured to store at least a portion of the first and second images as bitmaps within first and second latches, respectively, and wherein the processing circuitry includes a barrel-shifter configured to shift bits within at least one of the first latch or the second latch to align a portion of the first image with a portion of the second image based on the target area.

8. The device of claim 1 , wherein the processing circuitry is further configured to read at least one of the first image or the second image from the NVM array without error correction coding (ECC).

9. The device of claim 8 , wherein the processing circuitry is further configured to (a) receive an indication of a failed detection of the object within the second image and, in response to the indication, (b) re-store at least one of the first image or the second image in the NVM array while using ECC.

10. The device of claim 1 , wherein the processing circuitry is further configured to (a) receive an indication of a failed detection of the object within the second image and, in response to the indication, (b) re-store at least one of the first image or the second image in a different portion of the NVM array.

11. The device of claim 1 , wherein the NVM array is a multi-planar array and wherein the processing circuitry is further configured to concurrently insert a plurality of the objects into a corresponding plurality of images obtained from separate planes of the NVM array.

12. A method for use with a device formed on a die having a non-volatile memory (NVM) array, the method comprising:

obtaining a first image from the NVM array;

obtaining a second image corresponding to an object to be inserted into the first image;

identify pixels within a target area of the first image for the object to be inserted; and

inserting the object into the first image by inverting at least one bit within each of the identified pixels of the first image.

13. The method of claim 12 , wherein the inserting of the object into the first image by inverting at least one bit within each of the identified pixels of the first image comprises inverting all bits within each of the identified pixels of the first image.

14. The method of claim 13 , wherein the inverting of all the bits within each of the identified pixels of the first image comprises XORing the identified pixels with binary 1s.

15. The method of claim 12 , wherein the inserting of the object into the first image by inverting at least one bit within each of the identified pixels of the first image comprises inverting only a most significant bit (MSB) within each of the identified pixels of the first image is inverted.

16. The method of claim 12 , wherein the target area within the first image for insertion of the object is randomly determined.

17. The method of claim 12 , wherein the target area within the first image for insertion of the object is determined based on information obtained from a data storage controller.

18. The method of claim 12 , wherein at least a portion of the first and second images are stored as bitmaps within first and second latches, respectively, and wherein a barrel-shifter shifts the bits within at least one of the first or second latches to align a portion of the first image with a portion of the second image based on the target area.

19. The method of claim 12 , wherein at least one of the first image or the second image is read from the NVM array without error correction coding (ECC).

20. The method of claim 19 , wherein the method further comprises receiving an indication of a failed detection of the object within the second image and, in response to the indication, at least one of the first image or the second image are re-stored in the NVM array while using ECC.

21. The method of claim 12 , wherein the method further comprises receiving an indication of a failed detection of the object within the second image and, in response to the indication, at least one of the first image or the second image is re-stored in a different portion of the NVM array.

22. The method of claim 12 , wherein the NVM array is a multi-planar array and wherein the method is performed to concurrently insert a plurality of the objects into a corresponding plurality of images obtained from separate planes of the NVM array.

23. An apparatus formed on a die that includes a non-volatile memory (NVM) array, the apparatus comprising:

means for obtaining a first image from the NVM array;

means for obtaining a second image corresponding to an object to be inserted into the first image;

means for identifying pixels within the first image having locations within the first image that correspond to the object to be inserted; and

means for inserting the object into the first image by inverting at least one bit within each of the identified pixels of the first image.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2022
From: LINNEN, DANIEL JOSEPH; MUTHIAH, RAMANATHAN; PERIYANNAN, KIRUBAKARAN; THACKER, NIKITA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060280/0951 →