Self-adaptive program pulse width for programming 3D NAND memory
Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.
1. An apparatus, comprising:
a control circuit configured to connect to a set of memory cells, the control circuit is configured to program the set of memory cells to a plurality of data states, the control circuit is configured to:
in a first program phase, apply consecutive program pulses having a first common pulse width and consecutively increasing peak magnitudes to the set of memory cells;
during the first program phase, determine a number of program pulses used by the set of memory cells to transition between data states;
determine when the number of program pulses exceeds a threshold;
in response to the number of program pulses exceeding the threshold, begin a second program phase which applies consecutive program pulses having consecutively increasing pulse widths and consecutively increasing peak magnitudes to the set of memory cells;
during the second program phase, determine that a number of program pulses used by the set of memory cells to transition between data states does not exceed a respective threshold; and
in response to the number of program pulses not exceeding the respective threshold, begin a third program phase which applies consecutive program pulses having a second common pulse width and consecutively increasing peak magnitudes to the set of memory cells.
2. The apparatus of claim 1 , wherein the second common pulse width is greater than the first common pulse width.
3. The apparatus of claim 2 , wherein:
the second common pulse width is equal to a pulse width of a last program pulse of the second program phase.
4. The apparatus of claim 1 , wherein:
to determine when the number exceeds the threshold, the control circuit is configured to determine respective numbers of program pulses used by the set of memory cells to make different transitions between data states and to compare the respective numbers to the threshold.
5. The apparatus of claim 1 , wherein:
the threshold is higher for transitions between higher data states than for transitions between lower data states; and
the higher data states have higher verify voltages than the lower data states.
6. The apparatus of claim 1 , wherein:
the control circuit is configured to apply the consecutive program pulses having consecutively increasing pulse widths and consecutively increasing peak magnitudes to the set of memory cells until programming of the set of memory cells is completed.
7. The apparatus of claim 1 , wherein:
the data states are adjacent data states of the plurality of data states.
8. The apparatus of claim 1 , wherein:
the data states are non-adjacent data states of the plurality of data states.
9. The apparatus of claim 1 , wherein:
to determine the number of program pulses used by the set of memory cells to transition between the data states, the control circuit is configured to determine a difference between a number of program pulses use to complete programming to a first data state of the plurality of data states and a number of program pulses use to complete programming to a second data state of the plurality of data states.
10. The apparatus of claim 1 , wherein:
each memory cell of the set of memory cells is in a respective NAND string of a set of NAND strings;
the set of NAND strings is formed in memory holes in a block and extend vertically from a substrate; and
program speeds of the memory cells vary due to process variations of the block.
11. The apparatus of claim 10 , wherein:
the threshold varies as a function of a height of the set of memory cells above the substrate.
12. A method, comprising:
in a first program phase, applying consecutive program pulses having a first common pulse width and consecutively increasing peak magnitudes to a set of memory cells;
during the first program phase, determining a number of program pulses used to make a transition between data states and comparing the number to a respective threshold until a first transition is found in which the number exceeds a respective threshold;
in response to finding the first transition, starting a second program phase which applies consecutive program pulses having consecutively increasing pulse widths and consecutively increasing peak magnitudes to the set of memory cells;
during the second program phase, determining a number of program pulses used to make a transition between data states, comparing the number to a respective threshold, and determining that a second transition is not found in which the number exceeds the respective threshold; and
in response to not finding the second transition, applying consecutive program pulses having a second common pulse width and consecutively increasing peak magnitudes to the set of memory cells in a third program phase.
13. The method of claim 12 , wherein the second common pulse width is greater than the first common pulse width.
14. The method of claim 13 , wherein:
the second common pulse width is equal to a pulse width of a last program pulse of the second program phase.
15. The method of claim 12 , wherein:
the respective threshold differs for different transitions between data states.
16. An apparatus, comprising:
a control circuit configured to connect to a set of memory cells; and
an interface connected to the control circuit, the control circuit is configured to issue commands via the interface to:
in a first program phase, apply consecutive program pulses having a first common pulse width;
during the first program phase, determine that a first program speed of the set of memory cells is below a threshold;
in response to the determining that the first program speed is below the threshold, begin a second program phase in which additional programming is performed for the set of memory cells, the additional programming applies consecutive program pulses having consecutively increasing pulse widths;
during the second program phase, determine that a second program speed of the set of memory cells is below the threshold; and
in response to the determining that the second program speed is below the threshold, begin a third program phase in which additional programming is performed for the set of memory cells, the additional programming applies consecutive program pulses having a second common pulse width.
17. The apparatus of claim 16 , wherein:
the control circuit is configured to issue a command via the interface to compare the program speed of the set of memory cells to the threshold after each program pulse of the consecutive program pulses of the first program phase.
18. The apparatus of claim 16 , wherein:
the consecutive program pulses of the first program phase have consecutively increasing peak magnitudes; and
the consecutive program pulses of the second program phase have consecutively increasing peak magnitudes.
19. The apparatus of claim 16 , wherein:
during the first program phase, to determine that the program first speed of the set of memory cells is below the threshold, the control circuit is configured to issue a command via the interface to determine that a number of program pulses used to transition between data states exceeds a respective threshold.
20. The apparatus of claim 16 , wherein:
during the second program phase, the control circuit is configured to issue a command via the interface to apply the consecutive program pulses having the consecutively increasing pulse widths and consecutively increasing peak magnitudes to the set of memory cells until programming of the set of memory cells is completed.