Storage system and method for data protection during power loss
Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.
1. A storage system comprising:
a memory comprising data latches and a non-volatile memory array comprising single-level cell (SLC) memory and multi-level cell (MLC) memory; and
a controller configured to send a command to the memory in response to detection of power loss;
wherein in response to receiving the command, the memory is configured to abort an ongoing programming operation to program data, from the data latches, in the MLC memory, wherein after aborting the ongoing programming operation, some, but not all, memory cells in the MLC memory are successfully programmed; and
wherein the controller is further configured to:
store, in the SLC memory prior to powering down the storage system, data from the data latches that correspond to memory cells in the MLC memory that were not successfully programmed;
after powering up the storage system, reconstruct the data that was to be programmed in the MLC memory from the data stored in the SLC memory and from the memory cells in the MLC memory that were successfully programmed.
2. The storage system of claim 1 , wherein the controller is further configured to, after powering up the storage system, cause the data to be read from the SLC memory.
3. The storage system of claim 1 , wherein the ongoing programming operation is aborted without corrupting the data latches.
4. The storage system of claim 1 , wherein the memory is further configured to reconstruct the data one page at a time.
5. The storage system of claim 1 , wherein the controller is further configured to determine that a memory cell in the MLC memory was successfully programmed in response to determining its corresponding data latch indicates successful programming.
6. The storage system of claim 1 , wherein the controller is further configured to power down the storage system after storing the data in the SLC memory.
7. The storage system of claim 1 , further comprising a capacitor configured to power the storage system for shutdown operations in an absence of power from a host.
8. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.
9. In a storage system comprising a controller and a memory comprising data latches and a non-volatile memory array comprising single-level cell (SLC) memory and multi-level cell (MLC) memory, a method comprising:
sending a command from the controller to the memory in response to detection of power loss;
in response to the memory receiving the command, aborting an ongoing programming operation to program data, from the data latches, in the MLC memory, wherein after aborting the ongoing programming operation, some, but not all, memory cells in the MLC memory are successfully programmed; and
prior to powering down the storage system, programming, in the SLC memory, data from the data latches that correspond to memory cells in the MLC memory that were not successfully programmed; and
after powering up the storage system, reconstructing the data that was to be programmed in the MLC memory from the data stored in the SLC memory and from the memory cells in the MLC memory that were successfully programmed.
10. The method of claim 9 , further comprising, after powering up the storage system:
programming the reconstructed data in the MLC memory.
11. The method of claim 10 , further comprising error correcting the data read from the SLC memory.
12. The method of claim 9 , wherein the ongoing programming operation is aborted without corrupting the data latches.
13. The method of claim 9 , further comprising determining that a memory cell in the MLC memory was successfully programmed in response to determining its corresponding data latch indicates successful programming.
14. The method of claim 9 , further comprising powering down the storage system after programming the SLC memory.
15. The method of claim 9 , further comprising logging memory status information and information about write-aborted locations in the MLC memory.
16. A storage system comprising:
a memory comprising data latches and a non-volatile memory array comprising single-level cell (SLC) memory and multi-level cell (MLC) memory;
means for, in response to receiving a command generated in response to detection of power loss, aborting an ongoing programming operation to program data, from the data latches, in the MLC memory, wherein after aborting the ongoing programming operation, some, but not all, memory cells in the MLC memory are successfully programmed;
means for storing, in the SLC memory prior to powering down the storage system, data from the data latches that correspond to memory cells in the MLC memory that were not successfully programmed; and
means for, after powering up the storage system, reconstructing the data that was to be programmed in the MLC memory from the data stored in the SLC memory and from the memory cells in the MLC memory that were successfully programmed.
17. The storage system of claim 16 , further comprising:
means for programming the reconstructed data in the MLC memory.
18. The storage system of claim 16 , further comprising:
means for error correcting the data read from the SLC memory.
19. The storage system of claim 16 , further comprising a capacitor configured to power the storage system for shutdown operations in an absence of power from a host.