IP Library Granted Patent US 11,150,841
Granted Patent B2
US 11,150,841 · App. 16/786,889 · Granted Oct 19, 2021

NAND dropped command detection and recovery

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Quick Facts
Patent No.
US 11,150,841
App. No.
16/786,889
Granted
Oct 19, 2021
Kind
B2
Abstract

Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.

Claims (38)

1. A storage device, comprising:

memory configured to store data and a die status for a command associated with the data, the die status including one of a ready status or a busy status; and

a controller coupled to the memory and configured to:

receive, from a host device, the command associated with the data,

wait a time period, t DCDmin <=t<t DCDmax , after receiving the command to query the die status, wherein t DCDmin is a minimum time by which the command is expected to begin execution and t DCDmax is a maximum time by which the command is expected to complete execution,

query the die status after waiting the time period, and

detect whether the command associated with the data is dropped based on the die status.

2. The storage device of claim 1 , wherein the memory includes a plurality of memory locations controlled by one or more chip-enable (CE) signals, and the command associated with the data is for a memory location of the plurality of memory locations.

3. The storage device of claim 2 , wherein the controller is further configured to select the memory location using the one or more CE signals and to query the die status for the command after selecting the memory location.

4. The storage device of claim 3 , wherein the plurality of memory locations comprise dies sharing a single bus with the controller.

5. The storage device of claim 1 , wherein the controller is configured to detect that the command associated with the data is dropped and to subsequently request the host device to reissue the command when the die status is the ready status.

6. The storage device of claim 1 , wherein the controller is further configured to repeatedly poll the die status when the die status is the busy status until the die status becomes the ready status.

7. A storage device, comprising:

memory configured to store data and a die status for a command associated with the data, wherein the memory includes a plurality of memory locations controlled by one or more chip-enable (CE) signals; and

a controller configured to receive from a host device the command associated with the data for a memory location of the plurality of memory locations and to select the memory location using the one or more CE signals, the controller being further configured to wait a time period, t DCDmin <=t<t DCDmax , after receiving the command to query the die status,

wherein t DCDmin is a minimum time by which the command is expected to begin execution and t DCDmax is a minimum maximum time by which the command is expected to complete execution, and

wherein the controller is further configured to query the die status after waiting the time period and to detect whether the command associated with the data is dropped based on the die status, the die status including one of a ready status or a busy status.

8. The storage device of claim 7 , wherein the plurality of memory locations comprise a plurality of dies sharing a single bus with the controller.

9. The storage device of claim 8 , wherein the controller is configured to query the die status by one of:

sending status commands to one of the plurality of dies on the single bus; or

reading a busy wire of the one of the plurality of dies.

10. The storage device of claim 8 , wherein t DCDmin and t DCDmax are different for different dies of the plurality of dies.

11. The storage device of claim 7 , wherein the controller is configured to detect that the command associated with the data is dropped when the die status is the ready status.

12. The storage device of claim 11 , wherein the controller is further configured to request the host device to reissue the command when the die status is the ready status.

13. The storage device of claim 7 , wherein the controller is further configured to repeatedly poll the die status when the die status is the busy status until the die status becomes the ready status.

14. A storage device, comprising:

memory configured to store data and a die status for a command associated with the data, the die status including one of a ready status or a busy status; and

a controller configured to receive from a host device the command associated with the data, the controller being further configured to wait a time period, t DCDmin <=t<t DCDmax , after receiving the command to query the die status,

wherein t DCDmin is a minimum time by which the command is expected to begin execution and t DCDmax is a maximum time by which the command is expected to complete execution, and

wherein the controller is further configured to query the die status after waiting the time period, and to detect that the command associated with the data is dropped and request the host device to reissue the command when the die status is the ready status.

15. The storage device of claim 14 , wherein the memory includes a plurality of memory locations controlled by one or more chip-enable (CE) signals, and the command associated with the data is for a memory location of the plurality of memory locations.

16. The storage device of claim 15 , wherein the controller is further configured to select the memory location using the one or more CE signals and to query the die status for the command after selecting the memory location.

17. The storage device of claim 15 , wherein the plurality of memory locations comprise a plurality of dies sharing a single bus with the controller.

18. The storage device of claim 17 , wherein the controller is configured to query the die status by one of:

sending status commands to one of the plurality of dies on the single bus; or

reading a busy wire of the one of the plurality of dies.

19. The storage device of claim 17 , wherein t DCDmin and t DCDmax are different for different dies of the plurality of dies.

20. The storage device of claim 14 , wherein the controller is further configured to repeatedly poll the die status when the die status is the busy status until the die status becomes the ready status.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2020
From: ELLIS, ROBERT; O'TOOLE, KEVIN; SCHMIER, JACOB
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 051774/0744 →