Setting operating parameters for memory cells based on wordline address and cycle information
View Patent ↗Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.
1. A method for setting operating parameters in a storage device, comprising:
identifying, in connection with a memory operation, one or more wordlines associated with a plurality of flash memory cells;
determining that a current memory cycle condition associated with the plurality of flash memory cells satisfies a predetermined cycle condition;
setting one or more parameters of the memory operation based on one or more selected bias values, the bias values being selected based on the identified one or more wordlines and the current memory cycle condition satisfying the predetermined cycle condition; and
performing the memory operation using the set one or more parameters.
2. The method of claim 1 , wherein the current memory cycle condition is a current number of program/erase cycles, and wherein the predetermined cycle condition is a predetermined number of program/erase cycles.
3. The method of claim 2 , further comprising:
retrieving the one or more bias values from a stored location based on an indexing of a lookup table by one or more wordline addresses associated with the identified one or more wordlines and the current number of program/erase cycles.
4. The method of claim 3 , wherein the memory operation is a program operation and the one or more parameters comprise a program verify level.
5. The method of claim 3 , wherein the memory operation is a read operation and the one or more parameters comprise a read level.
6. The method of claim 3 , further comprising:
determining one or more current program level distributions for data stored in the plurality of flash memory cells; and
updating the one or more bias values in the stored location based on a difference between the determined one or more current program level distributions and predetermined expected values for predetermined programming levels for the current number of program/erase cycles.
7. The method of claim 1 , further comprising:
determining an error rate for the plurality of memory cells;
adjusting the one or more bias values based on a difference between the determined error rate and a predetermined error rate, the predetermined error rate being predetermined for the current memory cycle condition and the one or more wordlines.
8. The method of claim 7 , wherein the one or more bias values are increased if the determined error rate is greater than the predetermined error rate.
9. The method of claim 7 , wherein the one or more bias values are set to a default value if the determined error rate is lower than the predetermined error rate.
10. The method of claim 1 , wherein the current memory cycle condition is a current retention time associated with the plurality of memory cells, and wherein the predetermined cycle condition is a predetermined retention time.
11. The method of claim 1 , wherein setting one or more parameters of the memory operation comprises setting a first parameter for performing the memory operation on a first wordline of the one or more wordlines based on a first bias value, and setting a second parameter for performing the memory operation on a second wordline of the one or more wordlines based on a second bias value, the first and second bias values having different values.
12. A system, comprising:
one or more processors;
one or more flash memory; and
one or more memory media having bias values stored thereon, the one or more memory media having instructions stored thereon that, when executed by the one or more processors, cause the one or more processors to:
identify, in connection with a memory operation, one or more wordlines associated with a plurality of memory cells of the one or more flash memory;
determine that a current memory cycle condition associated with the plurality of memory cells satisfies a predetermined cycle condition;
set one or more parameters of the memory operation based on one or more selected bias values, the bias values being selected based on the identified one or more wordlines and the current memory cycle condition satisfying the predetermined cycle condition; and
perform the memory operation using the set one or more parameters.
13. The system of claim 12 , wherein the current memory cycle condition is a current number of program/erase cycles, and wherein the predetermined cycle condition is a predetermined number of program/erase cycles.
14. The method of claim 13 , wherein the instructions, when executed, further cause the one or more processors to:
retrieve the one or more bias values from a stored location based on an indexing of a lookup table by one or more wordline addresses associated with the identified one or more wordlines and the current number of program/erase cycles.
15. The system of claim 14 , wherein the memory operation is a program operation and the one or more parameters comprise a program verify level.
16. The system of claim 14 , wherein the memory operation is a read operation and the one or more parameters comprise a read level.
17. The system of claim 14 , wherein the instructions, when executed, further cause the one or more processors to:
determine an error rate for the plurality of memory cells;
adjust the one or more bias values based on a difference between the determined error rate and a predetermined error rate, the predetermined error rate being predetermined for the current memory cycle condition and the one or more wordlines.
18. The system of claim 12 , wherein the current memory cycle condition is a current retention time associated with the plurality of memory cells, and wherein the predetermined cycle condition is a predetermined retention time.
19. The system of claim 12 , wherein setting one or more parameters of the memory operation comprises setting a first parameter for performing the memory operation on a first wordline of the one or more wordlines based on a first bias value, and setting a second parameter for performing the memory operation on a second wordline of the one or more wordlines based on a second bias value, the first and second bias values having different values.
20. A machine-readable medium including machine-executable instructions thereon that, when executed by a computer or machine, perform a method, comprising:
identifying, in connection with a flash memory operation, one or more wordlines associated with a plurality of flash memory cells;
determining that a current memory cycle condition associated with the plurality of flash memory cells satisfies a predetermined cycle condition;
setting one or more parameters of the memory operation based on one or more selected bias values, the bias values being selected based on the identified one or more wordlines and the current memory cycle condition satisfying the predetermined cycle condition; and
performing the memory operation using the set one or more parameters.