System and method for processing and arbitrating submission and completion queues
Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.
1. A method for a memory device to process one or more commands, the method comprising:
fetching commands from one or more submission queues, a host device causing the commands to be stored in the one or more submission queues;
determining phases of processing for the commands from a plurality of phases of processing, wherein for each command the plurality of phases of processing comprises execution of the command, updating a completion queue indicative of completion of the command, or interrupting the host device indicative of updating the completion queue;
determining a priority of the commands based on the determined phases of processing; and
processing the commands based on the determined priority.
2. The method of claim 1 , wherein:
priority is higher for updating the completion queue and for interrupting the host device than for execution of the command.
3. The method of claim 1 , wherein the priority of the commands is predetermined and static based on a respective phase of processing for a respective command.
4. The method of claim 1 , wherein the priority of the commands is determined dynamically based on an analysis of current phases of the commands subject to processing.
5. The method of claim 1 , wherein:
the commands include read requests to the host device corresponding to actions in different phases of processing the commands; and
an order of performing the actions is determined based on priority of the read requests to the host device.
6. The method of claim 5 , wherein:
a first read request comprises data fetching to perform an action of fetching data from the host device;
a second read request comprises command fetching to perform an action of fetching a command from the host device; and
the first read request is assigned a higher priority than the second read request.
7. The method of claim 1 , wherein:
the commands include write requests to the host device corresponding to actions in different phases of processing the commands; and
an order of performing the actions is determined based on priority of the write requests to the host device.
8. The method of claim 7 , wherein:
a first write request comprises interrupt posting to perform an action of generating an interrupt to the host device;
a second write request comprises data writing to perform an action of writing data to the host device, wherein the data was read from non-volatile memory in the memory device; and
the first write request is assigned a higher priority than the second write request.
9. The method of claim 1 , wherein determining the priority of the commands based on the determined phases of processing comprises:
determining respective numbers of commands in respective phases of processing;
comparing the respective numbers of commands in the respective phases of processing with predetermined respective numbers assigned to the respective phases; and
prioritizing processing of the commands based on the comparison.
10. A non-volatile memory device comprising:
a non-volatile memory having a plurality of memory cells;
a communication interface configured to communicate with a host device; and
a controller in communication with the non-volatile memory and the communication interface, the controller configured to:
communicate with the host device regarding commands from one or more submission queues;
determine phases of processing for the commands from a plurality of phases of processing, wherein for each command the plurality of phases of processing comprises execution of the command, updating a completion queue indicative of completion of the command, or interrupting the host device indicative of updating the completion queue;
determine a priority of the commands based on the determined phases of processing; and
process the commands based on the determined priority.
11. The non-volatile memory device of claim 10 , wherein:
the controller is further configured to update the completion queue and to interrupt the host device with a higher priority than execution of the command.
12. The non-volatile memory device of claim 10 , wherein the controller is further configured to:
analyze current phases of the commands subject to processing; and
determine the priority of the commands based on the analysis.
13. The non-volatile memory device of claim 10 , wherein the priority of the commands is predetermined and static based on a respective phase of processing for a respective command.
14. The non-volatile memory device of claim 10 , wherein the controller is configured to determine priority of the commands dynamically based on an analysis of current phases of the commands subject to processing.
15. The non-volatile memory device of claim 10 , wherein:
the commands include read requests to the host device corresponding to actions in different phases of processing the commands; and
the controller is configured to determine an order of performing the actions based on priority of the read requests to the host device.
16. The non-volatile memory device of claim 15 , wherein:
a first read request comprises data fetching to perform an action of fetching data from the host device;
a second read request comprises command fetching to perform an action of fetching the command from the host device; and
the controller is configured to assign the first read request a higher priority than the second read request.
17. The non-volatile memory device of claim 10 , wherein:
the commands include write requests to the host device corresponding to actions in different phases of processing the commands; and
the controller is configured to determine an order of performing the actions based on priority of the write requests to the host device.
18. The non-volatile memory device of claim 17 , wherein:
a first write request comprises interrupt posting to perform an action of generating an interrupt to the host device;
a second write request comprises data writing to perform an action of writing data to the host device, wherein the data was read from non-volatile memory in the memory device; and
the controller is configured to assign the first write request a higher priority than the second write request.
19. The non-volatile memory device of claim 10 , wherein to determine the priority of the commands based on the determined phases of processing, the controller is further configured to:
determine respective numbers of commands in respective phases of processing;
compare the respective numbers of commands in the respective phases of processing with predetermined respective numbers assigned to the respective phases; and
prioritize processing of the commands based on the comparison.
20. A non-volatile memory device comprising:
a non-volatile memory having a plurality of memory cells;
interface means for communicating with a host device; and
means, in communication with the non-volatile memory and the interface means, for:
determining phases of processing of commands from the host device from a plurality of phases of processing;
prioritizing the commands based on the determined phases of processing; and
processing the commands based on the prioritization;
wherein for each command, the plurality of phases of processing comprises execution of the command, updating a completion queue indicative of completion of the command, or interrupting the host device indicative of updating the completion queue.