Determining bias information for offsetting operating variations in memory cells
View Patent ↗Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.
1. A method for providing memory cell bias information for offsetting operation variations in memory cells, comprising:
cycling a plurality of memory cells for one or more cycle intervals;
determining, for each cycle interval, a shift in program levels for the memory cells at one or more memory addresses resulting from the cycling;
determining, for each cycle interval, one or more bias values that when applied to a memory operation causes the memory operation to restore the program levels for memory cells at the one or more memory addresses to within a predetermined tolerance of one or more predetermined values for the cycle interval and the one or more memory addresses, the one or more predetermined values based on predetermined programming data;
associating, for each cycle interval, the one or more bias values with the one or more memory addresses; and
storing the determined bias values and associated memory addresses in a parameter storage location associated with a memory controller of a solid state storage device, the parameter storage location configured to be accessible during storage operations by the memory controller for retrieval of the stored bias values based on a current operation memory address and a current cycle interval.
2. The method of claim 1 , further comprising:
randomly selecting, before the cycling, the plurality of memory cells from a plurality of selected memory die, each die associated with a common origin of manufacture.
3. The method of claim 1 , wherein the memory addresses associated with the determined bias values are wordline addresses.
4. The method of claim 3 , further comprising:
identifying, for a cycle interval, wordline addresses associated with bias values within a predetermined deviation of each other;
grouping, for the cycle interval, the wordline addresses into one or more wordline groups based on the identifying; and
associating each wordline group with a group bias value, the group bias value being within the predetermined deviation of the bias values associated with the wordlines of the wordline group,
wherein the determined bias values stored in the parameter storage location comprise the group bias values.
5. The method of claim 1 , wherein the memory address associations are stored in a lookup table indexed by wordline addresses and cycle intervals.
6. The method of claim 1 , wherein the memory operation comprises a program verify operation, and wherein each determined bias value adjusts a program verify level.
7. The method of claim 1 , wherein the memory operation comprises a read operation, and wherein each determined bias value adjusts a read level.
8. The method of claim 1 , wherein determining the one or more bias values for a respective cycle interval comprises:
determining that the one or more bias values generate the lowest bit error rate at the cycle interval for each respective memory address compared to other bias values.
9. The method of claim 1 , wherein each cycle interval comprises a predetermined number of program/erase cycles.
10. The method of claim 1 , wherein each cycle interval comprises a predetermined memory retention time.
11. A non-transitory machine readable medium having instructions stored thereon that, when executed by a computer-enabled machine, case the machine to perform a method comprising:
cycling a plurality of memory cells at one or more memory addresses for one or more cycle intervals;
determining, for each cycle interval, a shift in program levels for the memory cells resulting from the cycling;
determining, for each cycle interval, one or more bias values that when applied to a memory operation causes the memory operation to restore the program levels for memory cells at the one or more memory addresses to within a predetermined tolerance of one or more predetermined values for the cycle interval and the one or more memory addresses, the one or more predetermined values based on predetermined programming data;
associating, for each cycle interval, the one or more bias values with the one or more memory addresses; and
storing the determined bias values and corresponding memory address associations in a parameter storage location associated with a memory controller of a solid state storage device, the parameter storage location configured to be accessible during storage operations by the memory controller for retrieval of the stored bias values based on a current operation memory address and a current cycle interval.
12. The machine readable medium of claim 11 , wherein the plurality of memory cells are randomly selected from a plurality of selected memory die, each die associated with a common origin of manufacture.
13. The machine readable medium of claim 11 , wherein the memory addresses associated with the determined bias values are wordline addresses.
14. The machine readable medium of claim 13 , the method further comprising:
identifying, for a cycle interval, wordline addresses associated with bias values within a predetermined deviation of each other;
grouping, for the cycle interval, the wordline addresses into one or more wordline groups based on the identifying; and
associating each wordline group with a group bias value, the group bias value being within the predetermined deviation of the bias values associated with the wordlines of the wordline group,
wherein the determined bias values stored in the parameter storage location comprise the group bias values.
15. The machine readable medium of claim 11 , wherein the memory address associations are stored in a lookup table indexed by wordline addresses and cycle intervals.
16. The machine readable medium of claim 11 , wherein the memory operation comprises a program verify operation, and wherein each determined bias value adjusts a program verify level.
17. The machine readable medium of claim 11 , wherein the memory operation comprises a read operation, and wherein each determined bias value adjusts a read level.
18. The machine readable medium of claim 11 , wherein determining the one or more bias values for a respective cycle interval comprises:
determining that the one or more bias values generate the lowest bit error rate for each respective memory address at the cycle interval compared to other bias values.
19. The machine readable medium of claim 11 , wherein each cycle interval comprises a predetermined number of program/erase cycles.
20. The machine readable medium of claim 11 , wherein each cycle interval comprises a predetermined memory retention time.