Non-volatile memory bitmap for garbage collection
Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.
1. An apparatus comprising:
one or more control circuits configured to communicate with a three-dimensional memory structure comprising non-volatile memory cells, the one or more control circuits configured to:
maintain a bitmap in the non-volatile memory cells, wherein bits in the bitmap map to addresses in the non-volatile memory cells, wherein each bit has either a first value to indicate that the corresponding address has valid data or a second value to indicate that the corresponding address does not have valid data, wherein maintaining the bitmap includes performing a bit-level erase operation on a first non-volatile memory cell in the bitmap to update a first bit in the bitmap to one of the first value or the second value responsive to a determination that data stored at a first address to which the first bit maps has changed in validity while inhibiting erase of a second non-volatile memory cell in the bitmap that is currently in an SLC (single-level cell) programmed state that represents the other of the first value or the second value, wherein inhibiting erase of the second non-volatile memory cell keeps validity status unchanged for data stored at a second address to which a second bit in the bitmap maps; and
perform garbage collection based on the bitmap.
2. The apparatus of claim 1 wherein, to maintain the bitmap, the one or more control circuits are further configured to:
identify first non-volatile memory cells in the bitmap to change from an SLC (single level cell) programmed state to an erase state in order to change validity of data units stored at addresses to which the first non-volatile memory cells map; and
perform a bit-level erase operation on the first non-volatile memory cells in the bitmap to change from the SLC programmed state to the erase state while inhibiting all other memory cells in the bitmap from erase.
3. The apparatus of claim 2 wherein, to maintain the bitmap, the one or more control circuits are further configured to:
identify second non-volatile memory cells in the bitmap to change from the erase state to the programmed state in order to change validity of data units stored at addresses to which the second non-volatile memory cells map; and
perform a bit-level program operation on the second non-volatile memory cells in the bitmap to change from the erase state to the programmed state while inhibiting all other memory cells in the bitmap from programming.
4. The apparatus of claim 1 wherein, to perform garbage collection, the one or more control circuits are further configured to:
determine whether respective non-volatile memory cells read for a portion of the bitmap corresponding to an erase block have a threshold voltage above or below a reference level; and
determine a count of invalid data units in the erase block based on the threshold voltages of the respective non-volatile memory cells.
5. The apparatus of claim 4 , wherein the apparatus comprises:
a memory structure die comprising the three-dimensional memory structure, wherein the non-volatile memory cells are NAND memory cells; and
a control die bonded to the memory structure die, wherein the control die comprises at least a portion of the one or more control circuits, the portion is configured to determine the count of invalid data units in the erase block based on the threshold voltages of the respective NAND memory cells.
6. The apparatus of claim 4 , wherein the apparatus comprises:
a memory die comprising the three-dimensional memory structure, wherein the non-volatile memory cells are NAND memory cells, wherein the memory die comprises at least a portion of the one or more control circuits, the portion is configured to determine the count of invalid data units in the erase block based on the threshold voltages of the respective NAND memory cells.
7. The apparatus of claim 1 wherein, to maintain the bitmap, the one or more control circuits are further configured to:
store a first version of the bitmap in a first group of NAND memory cells in the three-dimensional memory structure as unencoded data; and
store a second version of the bitmap in a second group of NAND memory cells in the three-dimensional memory structure as unencoded data;
read a portion of the first version of the bitmap from the first group;
read a corresponding portion of the second version of the bitmap from the second group;
compare bits in the first version with corresponding bits in the second version for consistency; and
use bits from a backup copy of the bitmap stored in a third group of NAND memory cells in the three-dimensional memory structure responsive to a determination of inconsistency between bits in the first version and second version.
8. The apparatus of claim 7 , wherein:
the second version of the bitmap is a one's complement to the first version of the bitmap.
9. The apparatus of claim 8 , wherein using the bits from the backup copy of the bitmap is performed by the one or more control circuits responsive to a failed status of a data integrity check of the backup copy with a complement of the backup copy of the bitmap.
10. A method for managing a NAND memory, the method comprising:
erasing an erase block in the NAND memory;
writing a unit of user data to a location in the erase block that is currently erased;
performing a first bit level memory operation to change a bit in a bitmap in the NAND memory from a first value to a second value responsive to the writing of the unit of the user data to the location in the erase block to indicate the unit of data stored at the location in the erase block is valid, including performing a bit-level erase to lower a threshold voltage of a first NAND memory cell in the bitmap that corresponds to the location in the erase block having the unit of valid user data while inhibiting erase of a second NAND memory cell in the bitmap that is currently in an SLC (single-level cell) programmed state and corresponds to another unit of data in the erase block that is not presently valid; and
performing a second bit level operation to change the bit in the bitmap in the NAND memory from the second value to the first value responsive to a determination that the unit of data at the location in the erase block is no longer valid.
11. The method of claim 10 , further comprising:
reading the bitmap from the NAND memory; and
performing garbage collection based on the bitmap.
12. The method of claim 10 , wherein performing the second bit level operation to change the bit in the bitmap from the second value to the first value comprises:
performing a bit-level program to increase the threshold voltage of the first NAND memory cell while inhibiting program of a third NAND memory cell in the bitmap that is currently erased and corresponds to another unit of data in the erase block that is presently valid.
13. A non-volatile storage system, the system comprising:
a three-dimensional memory structure comprising NAND memory cells; and
one or more control circuits in communication with the three-dimensional memory structure, the one or more control circuits configured to:
maintain a bitmap in the NAND memory cells, wherein bits in the bitmap map to addresses in the NAND memory cells, wherein each bit has either a first value to indicate that the corresponding address has valid data or a second value to indicate that the corresponding address does not have valid data, including:
store a first version of the bitmap in a first group of the NAND memory cells in the three-dimensional memory structure as unencoded data;
store a second version of the bitmap in a second group of the NAND memory cells in the three-dimensional memory structure as unencoded data;
read a portion of the first version of the bitmap from the first group;
read a corresponding portion of the second version of the bitmap from the second group;
compare bits in the first version with corresponding bits in the second version for consistency; and
use bits from a backup copy of the bitmap stored in a third group of the NAND memory cells in the three-dimensional memory structure responsive to a determination of inconsistency between bits in the first version and second version; and
perform garbage collection based on the backup copy of the bitmap.
14. The non-volatile storage system of claim 13 , wherein:
the second version of the bitmap is a one's complement to the first version of the bitmap.
15. The non-volatile storage system of claim 14 , wherein using the bits from the backup copy of the bitmap is performed by the one or more control circuits responsive to a failed status of a data integrity check of the backup copy with a complement of the backup copy of the bitmap.
16. The non-volatile storage system of claim 13 wherein, to perform the garbage collection, the one or more control circuits are further configured to:
determine whether respective non-volatile memory cells read for a portion of the backup copy of the bitmap corresponding to an erase block have a threshold voltage above or below a reference level; and
determine a count of invalid data units in the erase block based on the threshold voltages of the respective non-volatile memory cells.