IP Library Granted Patent US 9,082,492
Granted Patent B2
US 9,082,492 · App. 13/686,906 · Granted Jul 14, 2015

Nonvolatile memory device and memory management method thereof

Inventor: DongHun Kwak (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G11C16/107G11C16/105G11C16/16G11C16/3427H01L27/11582G11C16/0483
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Quick Facts
Patent No.
US 9,082,492
App. No.
13/686,906
Granted
Jul 14, 2015
Kind
B2
Abstract

Embodiments include a memory managing method of a nonvolatile memory device, which includes detecting whether sub-blocks of memory blocks are programmed, and programming write data at a memory block having a programmed sub-block from among the memory blocks, prior to programming a memory block having no programmed sub-blocks from among the memory blocks, according to the detection result. Embodiments also include programming the write data at a sub-block, closest to a common source line, from among unprogrammed sub-blocks of the memory block. Embodiments also include erasing at least one sub-block that is farthest from the common source line, prior to erasing other sub-blocks from among the programmed sub-blocks in the memory block. Embodiments also include selectively programming or erasing sub-blocks according to read merge times.

Claims (38)

1. A memory managing method of a nonvolatile memory device which comprises memory blocks having a three dimensional cell string structure, the memory blocks respectively comprise sub-blocks stacked in a direction perpendicular to a substrate, the method comprising:

detecting whether the sub-blocks of a memory block among the memory blocks are programmed; and

programming write data at the memory block according to the detection result,

wherein programming includes programming the write data at a sub-block, closest to a common source line, from among unprogrammed sub-blocks of the memory block,

the method further comprising:

reading merge times of the sub-blocks in the memory block;

determining a priority block to be a sub-block having an erase priority; and

selectively erasing the priority block from among the sub-blocks according to the read merge times.

2. The memory managing method of claim 1 , further comprising:

erasing at least one sub-block in the memory block according to the detection result.

3. The memory managing method of claim 2 , wherein:

the at least one sub-block is farthest from the common source line, from among programmed sub-blocks in the memory block; and

erasing includes erasing the at least one sub-block that is farthest from the common source line, prior to erasing other sub-blocks from among the programmed sub-blocks in the memory block.

4. The memory managing method of claim 3 , wherein the sub-blocks share the common source line.

5. The memory managing method of claim 1 , wherein determining includes determining the priority block according to relative distances between the common source line and the sub-blocks.

6. The memory managing method of claim 1 , wherein selectively erasing further comprises:

determining a merge time block to be a sub-block having a merge time shorter than that of the priority block of the memory block; and

comparing a merge time difference between the priority block and the merge time block with a predetermined value.

7. The memory managing method of claim 1 , further comprising reading out the merge times from a merge time table included in a flash translation layer.

8. A method for programming or erasing memory blocks which have a three dimensional cell string structure, the memory blocks respectively comprise sub-blocks stacked in a direction perpendicular to a substrate, the method comprising:

detecting which of the sub-blocks of the memory blocks are programmed;

detecting which of the sub-blocks of the memory blocks are unprogrammed;

determining that at least one of the memory blocks is a partial storage block having at least one programmed sub-block and at least one unprogrammed sub-block;

determining that at least one of the memory blocks is an empty storage block having no programmed sub-block; and

allocating and programming write data at the partial storage block prior to the empty storage block.

9. The method of claim 8 , further comprising:

detecting relative distances of sub-blocks of the plurality of memory blocks to a common source line; and

prioritizing the programming of the sub-blocks that are relatively closer to the common source line over the sub-blocks that are relatively farther away from the common source line.

10. The method of claim 9 , further comprising:

programming the sub-blocks that are relatively closer to the common source line prior to programming the sub-blocks that are relatively farther away from the common source line based on the prioritization.

11. The method of claim 9 , further comprising:

determining a priority block according to the relative distances of the sub-blocks of the plurality of memory blocks to the common source line and according to whether or not the sub-blocks in each of the memory blocks are programmed.

12. The method of claim 11 , further comprising:

programming the priority block.

13. The method of claim 8 , further comprising:

reading merge times of the sub-blocks in the memory blocks;

determining a priority block to be a sub-block having an erase priority; and

selectively erasing the priority block from among the sub-blocks according to the read merge times.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2012
From: KWAK, DONGHUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 029360/0159 →
Priority Claims (1)
KR 10-2012-0020506 · Feb 28, 2012 · national
Continuity (1)
Related Publication 20130223147A1 · Aug 29, 2013