IP Library Granted Patent US 11,875,038
Granted Patent B2
US 11,875,038 · App. 17/235,499 · Granted Jan 16, 2024

Block allocation for multi-CE/die structure SSD

Inventors: Min Young Kim (Suwon, KR); Min Woo Lee (Hwasung, KR); Dhayanithi Rajendiran (Milpitas, CA); Hiep Tran (Milpitas, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0619G06F3/0631G06F3/0644G06F3/0653G06F3/0679
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Quick Facts
Patent No.
US 11,875,038
App. No.
17/235,499
Granted
Jan 16, 2024
Kind
B2
Abstract

The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks. In certain embodiments, when there are insufficient free blocks in a free block list to replace a bad or defective block for a CE, an FTL scans blocks stored in an unallocated block repository. If there are unallocated blocks available for the CE, one or more is reallocated as free blocks and used to replace the bad or defective block. When only one or no further unallocated blocks for the CE are available, the FTL places the CE in a read-only mode.

Claims (54)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller comprises a configuration to execute a method for allocating blocks to replace one or more defective blocks in a solid state data storage device, the method comprising:

requesting, with a Flash Translation Layer (FTL), a free block for a first Chip Enable (CE) location from a first free block list responsive to a request to replace a defective block, wherein the first CE location comprises a plurality of NAND group locations;

scanning, with the FTL, the first free block list;

determining that the free block is not available from the first free block list to replace the defective block, wherein:

the first free block list is refilled from a queue of free blocks from an unallocated block pool storing a plurality of free blocks from a plurality of dies of the memory device, wherein the first free block list is a subset of the unallocated block pool and distinct from the unallocated block pool; and

refilling the first free block list comprises selecting a free block from the unallocated block pool that has a same CE location as a free block allocated from the free block list to refill the free block list;

determining that the free block is available from the unallocated block pool to replace the defective block;

replacing the defective block with the free block allocated from the unallocated block pool when the free block is available from the unallocated block pool, wherein the defective block remains in a read-write mode;

allocating the free block responsive to receiving a write command for the first CE location; and

programming data to the allocated free block, wherein the data is associated with the write command.

2. The data storage device of claim 1 , wherein the method, responsive to determining that the free block is available from the first free block list to replace the defective block, further comprises allocating the free block from the first free block list to replace the defective block.

3. The data storage device of claim 2 , wherein the method further comprises determining that the free block is from a CE location that is the same as the first CE location of the defective block.

4. The data storage device of claim 2 , the method further comprising decreasing a remaining block count for the first CE location.

5. The data storage device of claim 4 , the method further comprising replacing the defective block at the first CE location with the free block.

6. The data storage device of claim 1 , wherein the method, responsive to determining that the free block is not available from the unallocated block pool to replace the defective block, further comprises scanning a second unallocated block pool of the first CE location for a second free block.

7. The data storage device of claim 6 , the method further comprising transitioning the first CE location to a read only mode.

8. A controller for a data storage device, comprising:

an input/output (I/O) to one or more memory devices comprising computer-readable instructions;

a processor coupled to the one or more memory devices configured to execute the computer-readable instructions and cause the controller to perform a method for allocating blocks to replace one or more defective blocks in a data storage device, the method comprising:

scanning a first free block list associated with a Chip Enable (CE) location in the data storage device responsive to detecting a defective block, wherein the CE location comprises a plurality of NAND group locations;

determining that there are no free blocks in the first free block list to replace the defective block, wherein:

the first free block list is refilled from a queue of free blocks from an unallocated block pool, wherein the first free block list is a subset of the unallocated block pool and distinct from the unallocated block pool; and

refilling the first free block list comprises selecting a free block from the unallocated block pool that has a same CE location as a free block allocated from the first free block list to refill the free block list;

scanning an unallocated block pool for a free block;

replacing the defective block with the free block allocated from the unallocated block pool when the free block is available from the unallocated block pool, wherein the defective block remains in a read-write mode;

allocating the free block responsive to receiving a write command for the CE location; and

programming data to the allocated free block, wherein the data is associated with the write command.

9. The controller of claim 8 , wherein the computer-readable instructions further cause the processor to:

determine that the free block is available for the CE location; and

allocate the free block for the CE location.

10. The controller of claim 9 , wherein the computer-readable instructions further cause the processor to replace the defective block with the free block.

11. The controller of claim 10 , wherein the computer-readable instructions further cause the processor to increase a block count for the CE location.

12. The controller of claim 11 , wherein the computer-readable instructions further cause the processor to determine if the block count for the CE location is greater than or equal to a minimum remaining block count.

13. The controller of claim 8 , wherein the computer-readable instructions further cause the processor to determine that the free block is not available.

14. The controller of claim 13 , wherein the computer-readable instructions further cause the processor to transition the CE location to a read only mode.

15. A system for storing data, comprising:

one or more memory means; and

a controller means configured to perform a method for allocating blocks to replace one or more defective blocks in a solid state data storage device, the method comprising:

detecting a defective block in a Chip Enable (CE) location, wherein the CE location comprises a plurality of NAND group locations;

determining that a free block is available in a first free block list to replace the defective block, wherein:

the first free block list is refilled from a queue of free blocks from an unallocated block pool, wherein the first free block list is a subset of the unallocated block pool and distinct from the unallocated block pool;

refilling the first free block list comprises selecting a free block from the unallocated block pool that has a same CE location as a free block allocated from the first free block list to refill the free block list;

decreasing a remaining free block count associated with the first free block list;

determining that the remaining free block count of the first free block list is greater than or equal to a minimum remaining block count;

replacing the defective block with the free block from the first free block list when the free block is available from the free block list and the remaining free block count of the first free block list is greater than or equal to the minimum remaining block count, wherein the defective block remains in a read-write mode;

allocating the free block responsive to receiving a write command for the CE location; and

programming data to the allocated free block, wherein the data is associated with the write command.

16. The system of claim 15 , the method further comprising identifying the free_block in the CE location from an unallocated block pool.

17. The system of claim 16 , the method further comprising decreasing a remaining free block count associated with the unallocated block pool.

18. The system of claim 17 , the method further comprising providing the identified free block to replace the defective block.

19. The system of claim 15 , the method further comprising determining that there are no free blocks in an unallocated block pool.

20. The system of claim 19 , the method further comprising placing the CE location in a read-only mode.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2021
From: KIM, MIN YOUNG; LEE, MIN WOO; RAJENDIRAN, DHAYANITHI; TRAN, HIEP
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055979/0459 →
Continuity (1)
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