Mismatch compensation at differential signal receiver
A non-volatile memory module includes an input/output buffer coupled to first and second signal transmission paths, and control circuitry coupled to the input/output buffer, the control circuitry being configured to receive a first signal on the first signal transmission path, receive a second signal on the second signal transmission path, determine a delay between the first signal and the second signal, generate a delay mismatch value based on the determined delay, and transmit the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer.
1. A non-volatile memory module comprising:
an input/output buffer coupled to first and second signal transmission paths; and
control circuitry coupled to the input/output buffer, the control circuitry being configured to:
receive a first signal on the first signal transmission path from a controller chip communicatively coupled to the non-volatile memory module;
receive a second signal on the second signal transmission path from the controller chip;
determine a delay between the first signal and the second signal;
generate a delay mismatch value based on the determined delay;
transmit, to the controller chip, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
receive a true signal of a complementary signal pair on the first signal transmission path; and
receive a complementary signal of the complementary signal pair on the second signal transmission path;
wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
2. The non-volatile memory module of claim 1 , wherein the first and second signal transmission paths are at least partially integrated with a printed circuit board on which at least one of the non-volatile memory module and the controller chip is mounted.
3. The non-volatile memory module of claim 1 , wherein the control circuitry is further configured to determine the delay based on a difference in a receipt time associated with the first signal and a receipt time associated with the second signal.
4. The non-volatile memory module of claim 1 , wherein the first and second signals are pulse signals.
5. The non-volatile memory module of claim 1 , wherein the first signal is a true signal of a differential timing signal and the second signal is a complementary signal of the differential timing signal.
6. The non-volatile memory module of claim 1 , wherein:
the delay mismatch value is positive when the first signal is received prior to receiving the second signal; and
the delay mismatch value is negative when the second signal is received prior to receiving the first signal.
7. The non-volatile memory module of claim 1 , wherein the control circuitry is further configured to transmit the delay mismatch value as a digital signal.
8. The non-volatile memory module of claim 7 , wherein the delay mismatch value comprises a sequence of bits.
9. A method operational in a non-volatile memory module for compensating for a delay mismatch in signal transmission paths, the method comprising:
receiving, at an input/output buffer of the non-volatile memory module, a first signal on a first signal transmission path from a controller chip communicatively coupled to the non-volatile memory module;
receiving, at the input/output buffer of the non-volatile memory module, a second signal on a second signal transmission path from the controller chip;
determining a delay between the first signal and the second signal;
generating a delay mismatch value based on the determined delay;
transmitting, to the controller chip, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
receiving a true signal of a complementary signal pair on the first signal transmission path; and
receiving a complementary signal of the complementary signal pair on the second signal transmission path;
wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
10. The method of claim 9 , wherein said determining the delay is based on a difference in a receipt time associated with the first signal and a receipt time associated with the second signal.
11. The method of claim 9 , wherein the delay mismatch value is transmitted as a digital signal.
12. A computing device comprising:
an input/output buffer coupled to first and second signal transmission paths; and
control circuitry coupled to the input/output buffer, the control circuitry being configured to:
receive a first signal on the first signal transmission path from a computing module communicatively coupled to the computing device;
receive a second signal on the second signal transmission path from the computing module;
determine a delay between the first signal and the second signal;
generate a delay mismatch value based on the determined delay;
transmit, to the computing module, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
receive a true signal of a complementary signal pair on the first signal transmission path; and
receive a complementary signal of the complementary signal pair on the second signal transmission path;
wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
13. The computing device of claim 12 , wherein the first and second signal transmission paths are at least partially integrated with a printed circuit board on which at least one of the computing device and the computing module is mounted.
14. The computing device of claim 12 , wherein the control circuitry is further configured to determine the delay based on a difference in a receipt time associated with the first signal and a receipt time associated with the second signal.
15. The computing device of claim 12 , wherein the first and second signals are pulse signals.
16. The computing device of claim 12 , wherein the first signal is a true signal of a differential timing signal and the second signal is a complementary signal of the differential timing signal.
17. A non-volatile memory module comprising:
an input/output buffer coupled to first and second signal transmission paths and configured to receive, from a controller chip communicatively coupled to the non-volatile memory module, a first signal on the first signal transmission path and a second signal on the second signal transmission path; and
means for:
determining a delay between the first signal and the second signal;
generating a delay mismatch value based on the determined delay;
transmitting, to the controller chip, the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer;
receiving a true signal of a complementary signal pair on the first signal transmission path; and
receiving a complementary signal of the complementary signal pair on the second signal transmission path;
wherein one of the true signal and the complementary signal is delayed in accordance with the delay mismatch value.
18. The non-volatile memory module of claim 17 , wherein the delay is based on a difference in a receipt time associated with the first signal and a receipt time associated with the second signal.
19. The non-volatile memory module of claim 17 , wherein the first and second signals are pulse signals.
20. The non-volatile memory module of claim 17 , wherein the means for determining the delay comprises control circuitry of the non-volatile memory module.
21. The non-volatile memory module of claim 17 , wherein the first signal is a true signal of a differential timing signal and the second signal is a complementary signal of the differential timing signal.