High speed hard LDPC decoder
View Patent ↗The subject disclosure describes a method for performing error code correction, the method includes, loading a code word including a plurality of encoded bits into a memory array, initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits includes soft information. In certain aspects, the method further includes decoding the code word using the soft information and outputting the decoded code word from the memory array. A decoder and flash storage device are also provided.
1. A computer-implemented method for performing code word decoding, the method comprising:
loading a code word comprising a plurality of encoded bits into a memory array;
initializing, into one or more of a plurality of memory units, a plurality of bits associated with each of the encoded bits, wherein the plurality of bits initialized for each of the encoded bits is based on a value of the associated encoded bit and wherein the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits comprises soft information;
decoding the code word using the soft information; and
outputting the decoded code word from the memory array, without outputting the plurality of bits from the plurality of memory units.
2. The method of claim 1 , wherein initializing the plurality of bits associated with each of the encoded bits further comprises:
setting initial values for each of the plurality of bits based on a predetermined mapping corresponding with the value of the associated encoded bit.
3. The method of claim 1 , wherein each of the plurality of memory units comprises a variable node memory.
4. The method of claim 1 , wherein decoding the code word comprises LDPC decoding.
5. The method of claim 1 , wherein decoding the code word further comprises:
updating a value of one or more of the encoded bits in the memory array after each of a plurality of decoding cycles.
6. The method of claim 1 , wherein the memory array comprises an array of flip-flops.
7. A decoder for performing error correction on payload data, the decoder comprising:
a top bit array configured to store a code word comprising a plurality of encoded bits;
a plurality of memory units configured to store a plurality of bits initialized for each of the encoded bits; and
a plurality of processing units, wherein each of the processing units is coupled to the top bit array and to at least one of the plurality of memory units, and
wherein the plurality of processing units are configured to decode the code word using soft information comprising the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits.
8. The decoder of claim 7 , wherein the plurality of bits initialized for each of the encoded bits are based on a predetermined mapping.
9. The decoder of claim 7 , wherein each of the plurality of processing units are configured to update the soft information, based on one or more of the decoding cycles.
10. The decoder of claim 7 , wherein the plurality of processing units are configured to decode the code word using LDPC decoding.
11. The decoder of claim 7 , wherein the memory array comprises an array of flip-flops.
12. The decoder of claim 7 , wherein each of the plurality of memory units comprises a variable node memory.
13. A flash storage device, comprising:
a flash memory array;
a controller; and
a decoder coupled to the flash memory array and the controller, the decoder further comprising:
a top bit array configured to store a code word comprising a plurality of encoded bits;
a plurality of memory units configured to store a plurality of bits initialized for each of the encoded bits; and
a plurality of processing units, wherein each of the plurality of processing units is coupled to the top bit array and to at least one of the plurality of memory units, and
wherein each of the processing units is configured to decode the code word using soft information comprising the plurality of encoded bits and the plurality of bits initialized for each of the encoded bits.
14. The flash storage device of claim 13 , wherein the plurality of bits initialized for each of the encoded bits is based on a predetermined mapping.
15. The flash storage device of claim 13 , wherein each of the plurality of processing units are configured to update the code word after each of a plurality of decoding cycles.
16. The flash storage device of claim 13 , wherein each of the processing units is configured to decode the code word using LDPC decoding.
17. The flash storage device of claim 13 , wherein the memory array comprises an array of flip-flops.
18. The flash storage device of claim 13 , wherein each of the plurality of memory units comprises a variable node memory.