Thermal management of selector
A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.
1. A non-volatile memory device, comprising:
a word line;
a bit line disposed perpendicular to the word line;
a stack disposed between the word line and the bit line, wherein the stack comprises:
a memory element having a plurality of sides;
a selector having a plurality of sides; and
a spacer layer disposed between the memory element and the selector;
a heat sink dissipation layer adjacent to and surrounding the sides of the selector; and
a thermally insulating layer adjacent to and surrounding the sides of the memory element, wherein the thermally insulating layer is different from the heat sink dissipation layer.
2. The memory device of claim 1 , wherein the spacer layer comprises a material selected from the group consisting of TiN, TaN, TiSiN, TiAlN, Co, Ni, and Cu.
3. The memory device of claim 1 , wherein the bit line and word line comprises a material selected from the group consisting of Cu, Al, and W.
4. The memory device of claim 1 , wherein the stack further comprises one or more electrode contacts, the electrode contacts comprising a material selected from the group consisting of Ti, Ta, W, Al, Cr, Zr, Nb, Mo, Hf, B, C, carbon intermixed with other elements, conductive nitrides, and combinations thereof.
5. The memory device of claim 1 , wherein the memory element is selected from the group consisting of PCM, RRAM, MRAM and other temperature-generating memory elements.
6. The memory device of claim 1 , wherein the selector is selected from the group consisting of an ovonic threshold switch (OTS), doped-chalcogenide alloys, thin-film Si, and metal/metal-oxide switch.
7. The memory device of claim 1 , wherein the stack further comprises a first barrier layer between the spacer layer and the selector and a second barrier layer, wherein the selector is between the first barrier layer and the second barrier layer.
8. The memory device of claim 1 , wherein the selector comprises:
a plurality of sub-selector layers; and
one or more heat-sink layers, wherein the one or more heat sink layers are disposed between the sub-selector layers.
9. The memory device of claim 8 , wherein each of the one or more heat sink layers further comprises:
a first cobalt electromigration barrier;
a second cobalt electromigration barrier; and
a copper layer disposed between the first cobalt electromigration barrier and the second cobalt electromigration barrier.
10. The memory device of claim 1 , wherein the selector is selected from the group consisting of an ovonic threshold switch (OTS), doped-chalcogenide alloys, thin-film Si, and metal/metal-oxide switch.
11. The memory device of claim 1 , further comprising a second thermally insulating layer surrounding the heat sink dissipation layer.
12. The memory device of claim 1 , wherein the memory element comprises a PCM memory element.