IP Library Granted Patent US 11,347,420
Granted Patent B2
US 11,347,420 · App. 16/895,853 · Granted May 31, 2022

Attribute mapping in multiprotocol devices

Inventors: Ramanathan Muthiah (Karnataka, IN); Dinesh Kumar Agarwal (Karnataka, IN); Hitesh Golechchha (Karnataka, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/064G06F3/0604G06F3/0679G06F12/10
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Quick Facts
Patent No.
US 11,347,420
App. No.
16/895,853
Granted
May 31, 2022
Kind
B2
Abstract

Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.

Claims (26)

1. A storage device, comprising:

a memory including a plurality of blocks, wherein each of the blocks is associated with a storage attribute comprising an endurance level, a performance level, or a protection level;

a controller configured to receive a mapping of the storage attributes to different logical regions, to store the mapping in the memory during a first operation mode of the controller, to read the mapping from the memory during a second operation mode of the controller, and to map the plurality of blocks to logical addresses based on the mapping during the second operation mode, wherein the first operation mode comprises a non-volatile memory express (NVMe) mode, and the second operation mode comprises a Secure Digital (SD) mode.

2. The storage device of claim 1 , wherein the mapping is received from a host device.

3. The storage device of claim 1 , wherein the endurance level comprises a number of program/erase (P/E) cycles or a bit error rate (BER), the performance level comprises a latency of a program operation or a read operation, and the protection level comprises an exclusive-or (XOR) stripe length or a parity data size.

4. The storage device of claim 1 , wherein the memory comprises a non-volatile memory (NVM), and the controller is configured to store the mapping in the NVM.

5. The storage device of claim 1 , wherein the controller is further configured to identify a second mapping of the different logical regions to physical addresses based on the storage attributes during the first operation mode, and to store the second mapping in the memory during the first operation mode.

6. The storage device of claim 5 , wherein the controller is further configured to read the second mapping from the memory during the second operation mode, and to map the plurality of blocks to the logical addresses based on the second mapping during the second operation mode.

7. The storage device of claim 1 , wherein the controller is further configured to store host data in the plurality of blocks during the second operation mode based on the storage attributes.

8. A storage device, comprising:

a memory including a plurality of blocks, wherein each of the blocks is associated with a storage attribute comprising an endurance level, a performance level, or a protection level;

a controller configured to switch between a first operation mode and a second operation mode, to store in the memory a mapping of the storage attributes to different logical regions during the first operation mode, to read the mapping from the memory during the second operation mode, and to map the plurality of blocks to logical addresses based on the mapping during the second operation mode, wherein the first operation mode comprises a non-volatile memory express (NVMe) mode, and the second operation mode comprises a Secure Digital (SD) mode.

9. The storage device of claim 8 , wherein the controller is configured to switch between the first operation mode and the second operation mode in response to a command from a host device.

10. The storage device of claim 8 , wherein the controller is further configured to receive the mapping from a host device during the first operation mode.

11. The storage device of claim 8 , wherein the memory comprises a non-volatile memory (NVM) including the plurality of blocks, and the controller is configured to store the mapping in one of the blocks of the NVM.

12. The storage device of claim 8 , wherein the controller is further configured to identify during the first operation mode a second mapping of the different logical regions to physical addresses based on the storage attributes, and to store the second mapping in a block of the memory during the first operation mode.

13. The storage device of claim 12 , wherein the controller is further configured to read the second mapping from the block of the memory during the second operation mode, and to map the plurality of blocks to the logical addresses based on the second mapping during the second operation mode.

14. The storage device of claim 8 , wherein the controller is further configured to write host data to at least one of the blocks during the second operation mode based on the storage attributes.

15. A storage device, comprising:

a memory including a first plurality of blocks and a second plurality of blocks, wherein each of the first plurality of blocks and each of the second plurality of blocks is associated with a storage attribute comprising an endurance level, a performance level, or a protection level;

a controller configured to map the first plurality of blocks to logical addresses based on the storage attributes during a first operation mode of the controller, to store in the memory a mapping of the storage attributes to different logical regions during the first operation mode, to read the mapping from the memory during a second operation mode of the controller, and to map the second plurality of blocks to the logical addresses based on the mapping during the second operation mode, wherein the first operation mode comprises a non-volatile memory express (NVMe) mode, and the second operation mode comprises a Secure Digital (SD) mode.

16. The storage device of claim 15 , wherein the controller is configured to switch between the NVMe mode and the SD mode in response to a command from a host device.

17. The storage device of claim 16 , wherein the memory comprises a non-volatile memory (NVM), and the controller is configured to store the mapping in the NVM prior to switching to the SD mode.

18. The storage device of claim 15 , wherein the controller is further configured to identify a second mapping of the different logical regions to physical addresses based on the storage attributes during the first operation mode.

19. The storage device of claim 18 , wherein the controller is further configured to store the second mapping in the memory during the first operation mode, to read the second mapping from the memory during the second operation mode, and to map the second plurality of blocks to the logical addresses based on the second mapping during the second operation mode.

20. The storage device of claim 15 , wherein the controller is further configured to store host data in the second plurality of blocks during the second operation mode based on the storage attributes.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2020
From: MUTHIAH, RAMANATHAN; AGARWAL, DINESH KUMAR; GOLECHCHHA, HITESH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052989/0170 →