Debug data recovery after PLI event
The present disclosure generally relates to a storage device sensing critical failure or PLI events and writing the debug data to a memory device so that when boot-up occurs, at least some debug data is available. A dedicated hardware unit detects when one or more critical failure conditions occur by monitoring the one or more critical failure conditions. The critical failure conditions being detected or sensed triggers the dedicated hardware unit to automatically write debug data stored in a volatile memory device to a non-volatile memory device. The debug data stored in the non-volatile memory device provides a critical failure or PLI trace to determine what occurred leading up to and during a critical failure event. By writing the debug data to the non-volatile memory device, the critical failure trace may be accessed and analyzed after the device powers down or fails.
1. A data storage device, comprising:
a controller;
one or more volatile memory devices coupled to the controller;
one or more non-volatile memory devices coupled to the controller;
a power loss imminent circuit coupled to the controller; and
a dedicated hardware unit coupled to the power loss imminent circuit, the controller, the one or more non-volatile memory devices, and the one or more volatile memory devices, wherein the dedicated hardware unit is configured to:
detect one or more power loss imminent conditions from the power loss imminent circuit; and
write data stored in the one or more volatile memory devices to the one or more non-volatile memory devices when one or more of the power loss imminent conditions are detected, wherein the one or more non-volatile memory devices comprise one or more NAND memory devices and one or more NOR memory devices, and wherein the data is written to the one or more NOR memory devices when one or more of the power loss imminent conditions are detected.
2. The data storage device of claim 1 , wherein the one or more power loss imminent conditions comprise a temperature of the data storage device exceeding a predetermined operating temperature range.
3. The data storage device of claim 1 , wherein the one or more power loss imminent conditions comprise a voltage of the data storage device exceeding a predetermined operating voltage range.
4. The data storage device of claim 1 , wherein a first volatile memory device of the one or more volatile memory devices comprises a debug buffer for storing the data.
5. The data storage device of claim 4 , wherein a first non-volatile memory device of the one or more non-volatile memory devices comprises a dedicated pre-erased memory block.
6. The data storage device of claim 5 , wherein the dedicated hardware unit is further configured to write the data from the debug buffer of the first volatile memory device to the dedicated pre-erased memory block of the first non-volatile memory device when the power loss imminent circuit detects one or more power loss imminent conditions.
7. The data storage device of claim 1 , wherein the dedicated hardware unit is further configured to:
write data stored in the one or more volatile memory devices to the one or more non-volatile memory devices when the capacitor charge level is detected to reach the predetermined threshold;
write data stored in the one or more volatile memory devices to the one or more non-volatile memory devices when voltage conditions exceed a predetermined range; and
write data stored in the one or more volatile memory devices to the one or more non-volatile memory devices when temperature conditions exceed a predetermined range.
8. A data storage device, comprising:
a controller comprising one or more processors;
a power supply coupled to the controller, the power supply comprising one or more capacitors;
one or more non-volatile memory devices coupled to the controller, wherein at least one non-volatile memory device comprises a dedicated pre-erased erase block;
one or more volatile memory devices coupled to the controller, wherein at least one volatile memory device comprises a debug buffer for storing debug data; and
a dedicated hardware unit coupled to the controller and the one or more memory devices, wherein the dedicated hardware unit is configured to:
monitor a charge level of the one or more capacitors to detect when a capacitor charge level reaches a predetermined threshold; and
write debug data from the debug buffer of the at least one volatile memory device to the dedicated pre-erased erase block of the at least one non-volatile memory device when the capacitor charge level is detected to reach the predetermined threshold.
9. The data storage device of claim 8 , further comprising a power loss imminent circuit coupled to the dedicated hardware unit.
10. The data storage device of claim 9 , wherein the dedicated hardware unit is further configured to automatically detect one or more critical failure conditions from the power loss imminent circuit.
11. The data storage device of claim 8 , wherein the at least one non-volatile memory device is a NOR memory device, and wherein the debug data is written to the NOR memory device.
12. The data storage device of claim 11 , wherein the dedicated hardware unit is further configured to write a completion signal to the NOR memory device when all of the debug data is written to the NOR memory device.
13. The data storage device of claim 8 , wherein the dedicated hardware unit is further configured to:
monitor voltage conditions of the data storage device to determine whether the voltage conditions exceed a predetermined range, and
monitor temperature conditions of the data storage device to determine whether the temperature conditions exceed a predetermined range.
14. The data storage device of claim 13 , wherein the dedicated hardware unit is further configured to:
write debug data to the at least one non-volatile memory device when the voltage conditions exceed the predetermined range, and
write debug data to the at least one non-volatile memory device when the temperature conditions exceed the predetermined range.
15. The data storage device of claim 8 , wherein the at least one non-volatile memory device is a NOR memory device.
16. A method of operating a data storage device, comprising:
storing data in a volatile memory device;
monitoring one or more triggering critical failure conditions;
detecting when one or more of the triggering critical failure conditions occur; and
writing, by a dedicated hardware unit of the data storage device, the data the volatile memory device to a non-volatile memory device when one or more of the triggering critical failure conditions occur, wherein the non-volatile memory device is a NOR memory device, and wherein the data from the volatile memory device is written to a dedicated pre-erased memory block of the NOR memory device.
17. The method of claim 16 , further comprising powering down one or more processors when a power loss imminent process completes.
18. The method of claim 17 , wherein the power loss imminent process comprises writing data from write cache to a NAND memory device.
19. The method of claim 16 , wherein the one or more triggering critical failure conditions comprise a temperature of the data storage device exceeding a predetermined temperature range.
20. The method of claim 16 , wherein the one or more triggering critical failure conditions comprise a voltage of the data storage device exceeding a predetermined range.
21. The method of claim 16 , wherein the one or more triggering critical failure conditions comprise a power loss to the data storage device.
22. The method of claim 16 , wherein the NOR memory device comprises a dedicated pre-erased memory block, and wherein the data from the debug buffer of the volatile memory device is written to the dedicated pre-erased memory block of the NOR memory device.
23. A method of operating a data storage device, comprising:
storing debug data in a debug buffer of a volatile memory device, wherein the debug buffer continuously stores and updates the debug data;
detecting, by a dedicated hardware unit of the data storage device, one or more power loss imminent conditions;
writing, by the dedicated hardware unit, the debug data from the debug buffer to a dedicated pre-erased memory block of a non-volatile memory device when one or more of the power loss imminent conditions are detected, wherein the non-volatile memory device is a NOR memory device;
detecting a charge on a capacitor of the data storage device reaching a predetermined threshold; and
writing any remaining debug data from the debug buffer to the non-volatile memory device when the charge on the capacitor is detected to reach the predetermined threshold.
24. The method of claim 23 , wherein the power loss imminent conditions comprise an assert procedure being executed to the data storage device.
25. The method of claim 23 , further comprising monitoring, by the dedicated hardware unit, the debug buffer for new debug data stored.
26. The method of claim 23 , further comprising writing a completion signal to the dedicated memory block when all of the debug data is written to the non-volatile memory device.
27. The method of claim 23 , wherein the remaining debug data from the debug data buffer is written to the dedicated pre-erased memory block when the charge on the capacitor is detected to reach the predetermined threshold.
28. A data storage device, comprising:
a controller;
a plurality of memory devices coupled to the controller;
means for detecting one or more triggering critical failure conditions; and
means for automatically saving debug data when one or more of the triggering critical failure conditions are detected, wherein the means for automatically saving debug data when one or more of the triggering critical failure conditions are detected comprise writing debug data from a debug buffer of at least one volatile memory device of the plurality of memory devices to a dedicated pre-erased memory block of at least one NOR memory device of the plurality of memory devices.
29. The data storage device of claim 28 , wherein the plurality of memory devices comprise one or more NOR memory devices and one or more volatile memory devices, and wherein the at least one volatile memory device comprises a debug buffer for storing data.
30. The data storage device of claim 28 , wherein the one or more triggering critical failure conditions comprise a power loss to the data storage device.