IP Library Granted Patent US 12,417,180
Granted Patent B2
US 12,417,180 · App. 18/515,932 · Granted Sep 16, 2025

Cache write overlap handling

Inventor: Shay Benisty (Beer Sheva, IL)
Assignee: Sandisk Technologies, Inc.
G06F12/0815G06F3/061G06F3/0656G06F3/0679G06F12/0804G06F12/0855G06F12/0868G06F12/0871G06F2212/1024G06F2212/1032G06F2212/1056G06F2212/214G06F2212/312G06F2212/7203
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Quick Facts
Patent No.
US 12,417,180
App. No.
18/515,932
Granted
Sep 16, 2025
Kind
B2
Abstract

Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

Claims (32)

1. A data storage device, comprising:

a non-volatile memory;

means for detecting a cache collision;

means for ensuring that new write commands override prior write commands, wherein the means for ensuring that new write commands override prior write commands comprises a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer; and

a controller, wherein the controller is configured to:

detect a first accumulated buffer of the controller is available to empty to the non-volatile memory;

determine the first accumulated buffer is associated with an overlap stream;

delay the emptying of the first accumulated buffer to the non-volatile memory;

flush a second accumulated buffer associated with a random stream;

flush a third accumulated buffer associated with a sequential stream; and

empty the first accumulated buffer to the non-volatile memory.

2. The data storage device of claim 1 , wherein the non-volatile memory comprises a NAND flash memory.

3. The data storage device of claim 1 , further comprising means for classifying new write commands as random, sequential, or overlap.

4. The data storage device of claim 1 , further comprising means for detecting when the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer are available to empty to the non-volatile memory.

5. The data storage device of claim 1 , wherein the controller comprises:

the overlap accumulated buffer, the sequential accumulated buffer, and the random accumulated buffer.

6. The data storage device of claim 5 , further comprising a write command accelerator.

7. The data storage device of claim 1 , further comprising means to determine whether one or more write commands are classified as overlap write commands.

8. The data storage device of claim 1 , further comprising means to determine whether one or more write commands are classified as random write commands.

9. The data storage device of claim 1 , further comprising means to write data associated with a sequential write commands to the sequential accumulated buffer.

10. The data storage device of claim 1 , wherein the first accumulated buffer becomes available by meeting a pre-configured threshold of data.

11. The data storage device of claim 1 , wherein the first accumulated buffer becomes available when a flush request is received.

12. The data storage device of claim 1 , wherein the first accumulated buffer becomes available after a predetermined amount of time has passed.

13. The data storage device of claim 1 , wherein write commands are received for writing to the second accumulated buffer or the third accumulated buffer, and wherein the write commands for writing to the second accumulated buffer or the third accumulated buffer are received in a write command sequence prior to write commands for writing to the first accumulated buffer.

14. The data storage device of claim 1 , wherein the controller is further configured to:

detect a fourth accumulated buffer is available to empty to the non-volatile memory;

determine the fourth accumulated buffer is associated with one of the random stream or the sequential stream; and

flush the fourth accumulated buffer to the non-volatile memory.

15. The data storage device of claim 1 , wherein the controller is further configured to queue the accumulated buffers.

16. The data storage device of claim 1 , wherein the emptying occurs after the flushing.

17. The data storage device of claim 1 , wherein the delaying occurs prior to the flushing.

18. The data storage device of claim 1 , wherein the delaying occurs after the determining.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0284 →
PATENT COLLATERAL AGREEMENT (DDTL) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2023
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 065730/0813 →
Continuity (5)
Division 17860263 · Jul 8, 2022
Division 16925191 · Jul 9, 2020
Division 16003914 · Jun 8, 2018
Provisional Application 62518260 · Jun 12, 2017
Related Publication 20240086326A1 · Mar 14, 2024
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