IP Library Granted Patent US 11,281,399
Granted Patent B2
US 11,281,399 · App. 16/910,869 · Granted Mar 22, 2022

Dual-interface storage system and method for use therewith

Inventors: Shiva K (Bengaluru, IN); Eldhose Peter (Bengaluru, IN); Rakesh Balakrishnan (Bengaluru, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0658G06F3/0611G06F3/0635G06F3/0659G06F3/0683G06F13/4022
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Quick Facts
Patent No.
US 11,281,399
App. No.
16/910,869
Granted
Mar 22, 2022
Kind
B2
Abstract

A dual-interface storage system and method for use therewith are provided. In one embodiment, the storage system comprises a memory; a connector compatible with both a first host interface and a second host interface; a first data path to at least a part of the memory comprising the first host interface and a controller for the first host interface; a second data path to at least another part of the memory comprising the second host interface and a controller for the second host interface; and a switch configured to connect the connector to either the first data path or the second data path in response to a command from a host. Other embodiments are disclosed.

Claims (55)

1. A storage system comprising:

a memory;

a first host interface associated with a first protocol;

a first controller for the first host interface;

a second host interface associated with a second protocol;

a second controller for the second host interface;

a connector configured to connect with a host and compatible with both the first host interface and the second host interface; and

a switch configured to connect the connector to either a first data path or a second data path in response to a command from the host to direct the storage system to use the first data path or the second data path, wherein in response to the switch being connected to the first data path, the switch is disconnected from the second data path, and vice versa;

wherein:

the first data path connects the first host interface and the first controller for the first host interface to at least part of the memory; and

the second data path connects the second host interface and the second controller for the second host interface to at least another part of the memory.

2. The storage system of claim 1 , wherein:

the first host interface comprises a serial advanced technology attachment (SATA) interface; and

the second host interface comprises a peripheral component interconnect express (PCIe) interface.

3. The storage system of claim 1 , wherein the connector comprises a M.2 connector.

4. The storage system of claim 1 , wherein the switch is further configured to switch between the first data path and the second data path a plurality of times.

5. The storage system of claim 1 , wherein the switch is further configured to connect the connector to one of the first and second data paths by default upon power up.

6. The storage system of claim 1 , wherein:

the storage system is configured to detect a host capable of supporting only the first host interface or only the second host interface; and

the switch is further configured to connect the connector to the first data path or the second data path in response to that detection.

7. The storage system of claim 1 , wherein:

the host comprises an application layer, a driver layer, and a physical layer;

the storage system comprises a physical layer, a command layer, and a controller back-end layer.

8. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

9. A method comprising:

performing the following in a host in communication with a storage system comprising a memory, a first host interface associated with a first protocol, a second host interface associated with a second protocol, a first memory interface, a second memory interface, a connector configured to connect with the host and compatible with both the first host interface and the second host interface, and a switch:

determining whether to use the first host interface or the second host interface;

in response to determining to use the first host interface, sending a command to the storage system to cause the switch to connect the host with the first host interface, wherein a first data path connects the first host interface and a first controller for the first memory interface to at least part of the memory; and

in response to determining to use the second host interface, sending a command to the storage system to cause the switch to connect the host with the second host interface, wherein a second data path connects the second host interface and a second controller for the second memory interface to at least another part of the memory;

wherein in response to the switch being connected to the first data path, the switch is disconnected from the second data path, and vice versa.

10. The method of claim 9 , wherein:

the first host interface comprises a serial advanced technology attachment (SATA) interface; and

the second host interface comprises a peripheral component interconnect express (PCIe) interface.

11. The method of claim 9 , wherein the host comprises a connector compatible with both the first host interface and the second host interface.

12. The method of claim 11 , wherein the connector comprises a M.2 connector.

13. The method of claim 9 , wherein the host determines whether to use the first host interface or the second host interface based on power usage.

14. The method of claim 9 , wherein the host determines whether to use the first host interface or the second host interface based on which host application is accessing the storage system.

15. The method of claim 9 , further comprising sending commands to switch between the first and second host interfaces a plurality of times.

16. The method of claim 9 , wherein:

the host comprises an application layer, a driver layer, and a physical layer; and

the storage system comprises a physical layer, a command layer, and a controller back-end layer.

17. A storage system comprising:

a memory;

a first host interface associated with a first protocol;

a first controller for the first host interface;

a second host interface associated with a second protocol;

a second controller for the second host interface;

a connector configured to connect with a host and compatible with both the first host interface and the second host interface; and

means for switching between a first data path and a second data path in response to a command from the host to direct the storage system to use the first data path or the second data path, wherein when the first data path is used, the second data path is not used, and vice versa;

wherein:

the first data path connects the first host interface and the first controller for the first host interface to at least part of the memory; and

the second data path connects the second host interface and the second controller for the second host interface to at least another part of the memory.

18. The method of claim 9 , wherein the storage system further comprises a first controller for the first host interface and a second controller for the second host interface.

19. The method of claim 18 , wherein causing the switch to connect the host with the first host interface causes a connection between the first host interface and the first controller for the first host interface and at least part of the memory.

20. The method of claim 19 , wherein causing the switch to connect the host with the second host interface causes a connection between the second host interface and the second controller for the second host interface and at least another part of the memory.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: K, SHIVA; PETER, ELDHOSE; BALAKRISHNAN, RAKESH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053029/0001 →