Method and apparatus for write enable and inhibit for high density spin torque three dimensional (3D) memory arrays
View Patent ↗A method and apparatus for write enable and write inhibit for high density spin torque three dimensional (3D) memory arrays.
1. A two-dimensional planar nonvolatile memory array system, comprising:
a plurality of memory elements wherein each memory element stores at least one bit of data and formed between a top lead and a bottom lead, through which current is applied and travels, each memory element including,
a magnetic fixed layer formed between the top and bottom leads;
a magnetic free layer formed between the top and bottom leads; and
a non-magnetic spacer formed between the fixed and free layers; and
a memory controller operably coupled to the memory elements adapted to write data to the memory elements, wherein the memory controller is adapted to perform one or more of the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; or
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
2. The system of claim 1 , wherein the wherein the memory controller is adapted to perform the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; and
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
3. A nonvolatile memory array system, comprising:
a plurality of memory elements coupled, to form the array, through a single top lead and a single bottom lead, each memory element including a magnetic fixed layer and a magnetic free layer, separated by a spacer, wherein the direction of magnetization of the free layer, relative to the fixed layer, allows frequency addressing of the memory array; and
a memory controller operably coupled to the memory elements adapted to write data to the memory elements, wherein the memory controller is adapted to perform one or more of the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; or
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
4. The system of claim 3 , wherein the wherein the memory controller is adapted to perform the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; and
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
5. The system of claim 3 , wherein the memory elements of the plurality of memory elements are spin transfer torque memory elements.
6. A three-dimensional nonvolatile memory array system, comprising:
a plurality of memory elements arranged in a three-dimensional configuration wherein each memory element is selectable based on a unique resonant frequency; and
a memory controller operably coupled to the memory elements adapted to write data to the memory elements, wherein the memory controller is adapted to perform one or more of the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; or
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
7. The system of claim 6 , wherein the wherein the memory controller is adapted to perform the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; and
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
8. A method of writing to a nonvolatile memory array made of memory elements comprising:
receiving location information comprising:
one or more resonant frequencies of memory elements being written thereto; and
one or more resonant frequencies of memory elements not being written thereto; generating:
AC writing signals including frequency information based on the received location information, the frequency information including frequencies less than the resonant frequencies of memory elements being written thereto; and
AC writing inhibit signals including frequency information based on the received location information, the frequency information including frequencies greater than the resonant frequencies of memory elements not being written thereto;
frequency addressing the memory elements to be written to using the generated AC writing signals;
frequency addressing the memory elements not to be written to using the generated AC writing inhibit signals;
writing to the memory elements to be written thereto; and
inhibiting writing to the memory elements not to be written thereto.
9. The method of claim 8 , further comprising combining the generated AC signals with DC signals.
10. A method of writing to a nonvolatile memory array made of memory elements comprising:
receiving location information comprising one or more resonant frequencies of memory elements being written thereto;
generating AC writing signals including frequency information based on the received location information, the frequency information including frequencies less than the resonant frequencies of memory elements being written thereto;
frequency addressing the memory elements to be written to using the generated AC writing signals; and
writing to the memory elements to be written thereto.
11. The method of claim 10 , further comprising combining the generated AC signals with DC signals.
12. A method of inhibiting writing to a nonvolatile memory array made of memory elements comprising:
receiving location information comprising one or more resonant frequencies of memory elements not being written thereto;
generating AC writing inhibit signals including frequency information based on the received location information, the frequency information including frequencies greater than the resonant frequencies of memory elements not being written thereto;
frequency addressing the memory elements not to be written to using the generated AC writing inhibit signals; and
inhibiting writing to the memory elements not to be written thereto.
13. The method of claim 12 , further comprising combining the generated AC signals with DC signals.
14. A memory controller system for a nonvolatile memory system comprising one or more nonvolatile memory elements, comprising:
a memory controller adapted to be operably coupled to the memory elements and further adapted to write data to the memory elements, wherein the memory controller is adapted to perform one or more of the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than resonant frequencies of the memory elements to be written to; or
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.
15. The system of claim 14 , wherein the wherein the memory controller is adapted to perform the following:
write to one or more of the memory elements by applying signals to the one or more memory elements to be written to having frequencies that are less than the resonant frequencies of the memory elements to be written to; and
inhibit writing to one or more of the memory elements by applying signals to the one or more memory elements not to be written to having frequencies that are more than the resonant frequencies of the memory elements not to be written to.