Local data compaction for integrated memory assembly
An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
1. An apparatus, comprising:
a first semiconductor die comprising non-volatile memory cells and a first plurality of pathways; and
a second semiconductor die comprising one or more control circuits, the second semiconductor die further comprises an interface to an off die circuit and a second plurality of pathways directly connected to the first plurality of pathways, the second semiconductor die is directly bonded to the first semiconductor die, the one or more control circuits are configured to transfer signals through pathway pairs of the first plurality of pathways and the second plurality of pathways, the one or more control circuits are configured to:
read data from a first grouping of non-volatile memory cells of the first semiconductor die,
compact the data read to remove one or more gaps in valid data, and
program the compacted data to a second grouping of non-volatile memory cells of the first semiconductor die.
2. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to access a validity map for the first grouping of non-volatile memory cells of the first semiconductor die, the validity map indicates which subsets of data stored in the first grouping of non-volatile memory cells are valid and which subsets of data stored in the first grouping of non-volatile memory cells are invalid;
the one or more control circuits are further configured to choose valid subsets of the data read based on the validity map; and
the one or more control circuits are configured to compact the data read by removing invalid data and forming a unit of programming that comprises the chosen valid subsets of the data read.
3. The apparatus of claim 2 , wherein:
the one or more control circuits are further configured to store the compacted data by programming the unit of programming into the next open location in the second grouping of non-volatile memory cells.
4. The apparatus of claim 2 , wherein:
the one or more control circuits are further configured to decode the chosen valid subsets of the data to reduce errors in the chosen valid subsets of the data; and
the one or more control circuits are configured to re-encode the chosen valid subsets of the data prior to storing on the first semiconductor die.
5. The apparatus of claim 2 , wherein:
the one or more control circuits are further configured to determine a measure of error for the chosen valid subsets of the data;
the one or more control circuits are configured to store the unit of programming that comprises the chosen valid subsets of the data read without decoding and re-encoding the chosen valid subsets of the data if the measure of error is less than a first threshold; and
the one or more control circuits are configured to decode the chosen valid subsets of the data to reduce errors in the chosen valid subsets of the data and re-encode the chosen valid subsets of the data prior to storing on the unit of programming that comprises the chosen valid subsets of the data if the measure of error is greater than the first threshold.
6. The apparatus of claim 5 , wherein:
the one or more control circuits are configured to transfer chosen valid subsets of the data to a memory controller for decoding if the measure of error is greater than a second threshold that is higher than the first threshold.
7. The apparatus of claim 5 , wherein:
the measure of error is syndrome weight.
8. The apparatus of claim 2 , wherein: the one or more control circuits are further configured to receive a data compaction command and the validity map from a memory controller that is external to and separate from the first semiconductor die and the second semiconductor die; and the one or more control circuits are further configured to perform the reading of the data from the first grouping of non-volatile memory cells, compacting the data read and storing the compacted data in response to the data compaction command.
9. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to access a validity map for the first grouping of non-volatile memory cells of the first semiconductor die, the validity map indicates which subsets of data stored in the first grouping of non-volatile memory cells are valid and which subsets of data stored in the first grouping of non-volatile memory cells are invalid; and
the one or more control circuits are configured to read data from the first grouping of non-volatile memory cells and compact the data read by:
performing one or more sensing operations on the first grouping of non-volatile memory cells to read a first unit of read data, the first unit of read data includes multiple fragments,
choosing valid fragments from the first unit of read data based on the validity map and storing the chosen valid fragments on the second semiconductor die,
if the chosen valid fragments from the first unit of read data complete a unit of programming, then storing the unit of programming that includes the chosen valid fragments from the first unit of read data in the second grouping of non-volatile memory cells of the first semiconductor die, and
if the chosen valid fragments do not complete the unit of programming, then performing one or more sensing operations on the first grouping of non-volatile memory cells to read a second unit of data, choosing one or more valid fragments from the second unit of read data based on the validity map and combining the chosen one or more valid fragments from the second unit of read data with the chosen valid fragments from the first unit of read data to from a complete unit of programming and storing the complete unit of programming in the second grouping of non-volatile memory cells of the first semiconductor die.
10. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to access a validity map for the first grouping of non-volatile memory cells of the first semiconductor die, the validity map indicates which fragments of data stored in the first grouping of non-volatile memory cells are valid and which fragments of data stored in the first grouping of non-volatile memory cells are invalid;
the one or more control circuits are configured to read data from the first grouping of non-volatile memory cells by reading one or more pages of data from a source block;
the one or more control circuits are further configured to choose valid fragments of the one or more pages of data read based on the validity map;
the one or more control circuits are configured to compact the data read by removing invalid fragments and forming a new page of data that comprises the chosen valid fragments of the data read; and
the one or more control circuits are configured to store the compacted data by programming the new page of data to a destination block on the first semiconductor die.
11. The apparatus of claim 1 , wherein:
the one or more control circuits are further configured to receive a data compaction command from a memory controller that is external to and separate from the first semiconductor die and the second semiconductor die;
the one or more control circuits are further configured to perform the reading of the data from the first grouping of non-volatile memory cells, compacting the data read and storing the compacted data in response to the data compaction command; and
the one or more control circuits are further configured to perform the reading of the data from the first grouping of non-volatile memory cells, compacting the data read and storing the compacted data without transferring the data read to the memory controller.
12. The apparatus of claim 11 , wherein:
the one or more control circuits are further configured to receive a data compaction command and an indication of a location in the non-volatile memory cells of a validity map from a memory controller that is external to and separate from the first semiconductor die and the second semiconductor die;
the one or more control circuits are further configured to fetch the validity map from the location in the non-volatile memory cells, the validity map indicates which subsets of data stored in the first grouping of non-volatile memory cells are valid and which subsets of data stored in the first grouping of non-volatile memory cells are invalid;
the one or more control circuits are further configured to choose valid subsets of the data read based on the validity map; and
the one or more control circuits are configured to compact the data read by removing invalid data and forming a unit of programming that comprises the chosen valid subsets of the data read.
13. The apparatus of claim 1 , wherein:
the one or more control circuits are configured to read data from the first grouping of non-volatile memory cells of the first semiconductor die via the pathway pairs of the first plurality of pathways and the second plurality of pathways; and
the one or more control circuits are configured to store the compacted data by programming the compacted data via the pathway pairs of the first plurality of pathways and the second plurality of pathways.
14. The apparatus of claim 1 , wherein:
the second semiconductor die includes sense amplifiers for reading data from the non-volatile memory cells on the first semiconductor die.
15. The apparatus of claim 14 , wherein:
the non-volatile memory cells on the first semiconductor die are arranged in a memory array;
the memory array includes word lines;
the second semiconductor die includes address decoders for the memory array; and
the second semiconductor die includes signal generators configured to generate voltages applied to the word lines of the memory array.