Error recovery handling
A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.
1. A device comprising:
at least one processor configured to:
receive an error recovery request comprising error type information and an address of a page of a flash memory circuit for which a read error has occurred, wherein the error type information of the error recovery request is mapped to a first error recovery technique;
determine whether an error count associated with the flash memory circuit satisfies a first criterion and a block error map associated with the flash memory circuit satisfies a second criterion, wherein the error count indicates a number of read errors that have occurred on the flash memory circuit and the block error map indicates one or more blocks of the flash memory circuit in which the read errors have occurred; and
utilize a second error recovery technique to attempt to recover data stored in the page when the first and second criterions are satisfied, otherwise utilize the first error recovery technique to attempt to recover the data stored in the page, wherein the second error recovery technique is associated with recovering data stored in an offline flash memory circuit.
2. The device of claim 1 , wherein the at least one processor is further configured to:
utilize the second error recovery technique to attempt to recover the data stored in the page when the first and second criterions are satisfied irrespective of whether the flash memory circuit is offline.
3. The device of claim 1 , wherein the second error recovery technique differs from the first error recovery technique.
4. The device of claim 1 , wherein the at least one processor is further configured to:
increment the error count associated with the flash memory circuit prior to determining whether the error count satisfies the first criterion.
5. The device of claim 4 , wherein the at least one processor is further configured to:
determine a block of the flash memory circuit that includes the page; and
update the block error map associated with the flash memory circuit to reflect that the read error occurred in the block of the flash memory circuit prior to determining whether the block error map associated with the flash memory circuit satisfies the second criterion.
6. The device of claim 1 , wherein the at least one processor is further configured to:
determine whether the flash memory circuit has been marked as potentially offline when the first and second criterions are satisfied; and
mark the flash memory circuit as offline when the first and second criterions are satisfied and the flash memory circuit has been marked as potentially offline, otherwise mark the flash memory circuit as potentially offline when the first and second criterions are satisfied and the flash memory circuit has not been marked as potentially offline.
7. The device of claim 6 , wherein the at least one processor is further configured to:
determine, responsive to receipt of the error recovery request, whether the flash memory circuit is marked as offline; and
utilize the second error recovery technique to attempt to recover the page when the flash memory circuit is marked as offline without determining whether the first and second criterions are satisfied.
8. The device of claim 1 , wherein the at least one processor is further configured to:
reset, on a periodic basis, the error count associated with the flash memory circuit and the block error map associated with the flash memory circuit.
9. The device of claim 1 , further comprising a memory configured to store the error count associated with the flash memory circuit and the block error map associated with the flash memory circuit, wherein the block error map associated with the flash memory circuit comprises a bitmap.
10. The device of claim 1 , wherein the at least one processor is further configured to:
determine whether the error count associated with the flash memory circuit satisfies the first criterion prior to determining whether the block error map associated with the flash memory circuit satisfies the second criterion; and
bypass determining whether the block error map satisfies the second criterion when the error count fails to satisfy the first criterion.
11. The device of claim 1 , wherein the at least one processor is further configured to:
determine that the error count associated with the flash memory circuit satisfies the first criterion when the error count associated with the flash memory circuit exceeds a first threshold; and
determine that the block error map associated with the flash memory circuit satisfies the second criterion when the block error map indicates that at least a number of the one or more blocks of the flash memory circuit in which the read errors have occurred exceeds a second threshold.
12. A computer-implemented method comprising:
receiving, by a controller of a flash memory circuit, an error recovery request corresponding to a page of the flash memory circuit, wherein the error recovery request indicates an error type that is mapped to a first error recovery technique;
retrieving, by the controller, an error count associated with the flash memory circuit and a block error map associated with the flash memory circuit, wherein the error count indicates a number of read errors that have occurred on the flash memory circuit and the block error map indicates one or more blocks of the flash memory circuit in which the read errors have occurred;
determining, by the controller, a likelihood that data stored in the page of the flash memory circuit can be recovered using the first error recovery technique based at least in part on the error count and the block error map;
when the likelihood that the data stored in the page of the flash memory circuit can be recovered using the first error recovery technique satisfies a criterion, utilizing, by the controller, the first error recovery technique to attempt to recover the data stored in the page of the flash memory circuit, otherwise utilizing a second error recovery technique to attempt to recover the data stored in the page of the flash memory circuit without utilizing the first error recovery technique; and
determining that the likelihood that the data stored in the page of the flash memory circuit can be recovered using the first error recovery technique satisfies the criterion when the error count is below a first threshold and a number of the one or more blocks of the flash memory circuit in which the read errors have occurred is below a second threshold.
13. The computer-implemented method of claim 12 , further comprising:
setting, at predetermined intervals, the error count associated with the flash memory circuit to zero and clearing, at the predetermined intervals, the block error map associated with the flash memory circuit.
14. The computer-implemented method of claim 12 , wherein the first error recovery technique is different than the second error recovery technique.
15. The computer-implemented method of claim 14 , wherein the second error recovery technique is associated with recovering data stored in an offline flash memory circuit.
16. The computer-implemented method of claim 15 , wherein the second error recovery technique comprises a redundant array of independent disks (RAID) recovery technique.
17. The computer-implemented method of claim 12 , further comprising:
storing, by the controller, an indication that the flash memory circuit is unavailable for error recovery when the likelihood that the data stored in the page of the flash memory circuit can be recovered using the first error recovery technique fails to satisfy the criterion.
18. A system comprising:
flash memory circuits each comprising blocks, each of the blocks including one or more pages;
a random access memory (RAM) configured to store: a mapping between error types and error recovery techniques, an error count for each of the flash memory circuits, and a block error map for each of the flash memory circuits, wherein the error count for each respective flash memory circuit indicates a number of read errors that have occurred on each respective flash memory circuit and the block error map for each respective flash memory circuit indicates each of the blocks of each respective flash memory circuit in which at least one of the read errors has occurred;
an interface communicatively coupled to a host device; and
a controller configured to:
receive error recovery requests corresponding to read errors that have occurred on the flash memory circuits, each of the error recovery requests indicating a page of one of the flash memory circuits and one of the error types; and
for each of the error recovery requests:
identify one of the error recovery techniques mapped to the one of the error types;
determine whether the error count for the one of the flash memory circuits on which the corresponding read error occurred exceeds a first threshold and whether the block error map for the one of the flash memory circuits indicates that the read errors occurred in at least a number of the blocks of the one of the flash memory circuits; and
utilize another one of the error recovery techniques to attempt to recover data stored in the page when the error count exceeds the first threshold and the block error map indicates that the read errors occurred in the at least the number of the blocks, otherwise utilize the one of the error recovery techniques to attempt to recover the data stored in the page.
19. The system of claim 18 , wherein the controller is further configured to:
reset, at periodic intervals, the error count and the block error map for each of the flash memory circuits.
20. A system comprising:
means for receiving an error recovery request comprising error type information and an address of a page of a flash memory circuit for which a read error has occurred, wherein the error type information of the error recovery request is mapped to a first error recovery technique;
means for determining whether an error count associated with the flash memory circuit satisfies a first criterion and a block error map associated with the flash memory circuit satisfies a second criterion, wherein the error count indicates a number of read errors that have occurred on the flash memory circuit and the block error map indicates one or more blocks of the flash memory circuit in which the read errors have occurred; and
means for utilizing a second error recovery technique to attempt to recover data stored in the page when the first and second criterions are satisfied, otherwise utilizing the first error recovery technique to attempt to recover the data stored in the page, wherein the second error recovery technique is associated with recovering data stored in an offline flash memory circuit.