IP Library Granted Patent US 10,229,048
Granted Patent B2
US 10,229,048 · App. 15/197,116 · Granted Mar 12, 2019

Unified paging scheme for dense and sparse translation tables on flash storage systems

Inventors: Ajith Kumar Battaje (Karnataka, IN); Tanay Goel (Chhattisgarh, IN); Sandeep Sharma (Karnataka, IN); Saurabh Manchanda (Delhi, IN); Arun Kumar Medapati (Andhra Pradesh, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0246G06F12/1009G06F17/30958G06F2212/1016G06F2212/1056G06F2212/152G06F2212/214G06F2212/657G06F2212/7201G06F2212/7202
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Quick Facts
Patent No.
US 10,229,048
App. No.
15/197,116
Granted
Mar 12, 2019
Kind
B2
Abstract

A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a first translation table entry for a logical block, map the first translation table entry to a first dump unit, the first dump unit included in an array of dump units, identify a second translation table entry for the logical block in the first dump unit, the second translation table entry also being stored in a storage device, and generate a linked list in the storage device from the second translation table entry associated with the first dump unit, the linked list identifying previous translation table entries associated with the logical block.

Claims (60)

1. A method comprising:

receiving a first translation table entry for a logical block;

mapping the first translation table entry to a first dump unit, the first dump unit included in an array of dump units;

identifying a second translation table entry for the logical block in the first dump unit, the second translation table entry being stored in a storage device; and

generating a linked list in the storage device from the second translation table entry associated with the first dump unit, the linked list identifying previous translation table entries associated with the logical block.

2. The method of claim 1 , wherein the mapping of the first translation table entry to the first dump unit is based on a hash function, the mapping of the first translation table entry to the first dump unit being a hash of a logical block number of the logical block of the first translation table entry.

3. The method of claim 1 , further comprising:

allocating a space in memory for the array of dump units.

4. The method of claim 1 , wherein mapping includes storing the first translation table entry in the first dump unit.

5. The method of claim 1 , further comprising:

storing the first translation table entry in a logical space in memory.

6. The method of claim 1 , wherein the linked list includes updates to the logical block in a reverse chronological order, a most recent update being at a front of the linked list.

7. The method of claim 1 , further comprising:

grouping the array of dump units into a plurality of dump groups; and

assigning a fixed range of logical space in memory to each dump group in the plurality of dump groups.

8. The method of claim 1 , further comprising:

receiving a write request for the logical block, the write request including a new translation table entry for the logical block;

identifying the first dump unit associated with the logical block;

updating the second translation table entry in the storage device with the first translation table entry from the first dump unit;

storing the new translation table entry in the first dump unit; and

updating the linked list in the storage device, the linked list referencing the first translation table entry in the storage device through previous translation table entries associated with the logical block.

9. The method of claim 1 , further comprising:

eliminating duplicate entries for the logical block to get a consolidated representation of translation table entries on the storage device.

10. A system comprising:

a processor; and

a memory storing instructions that, when executed, cause the system to:

receive a first translation table entry for a logical block;

map the first translation table entry to a first dump unit, the first dump unit included in an array of dump units;

identify a second translation table entry for the logical block in the first dump unit, the second translation table entry being stored in a storage device; and

generate a linked list in the storage device from the second translation table entry associated with the first dump unit, the linked list identifying previous translation table entries associated with the logical block.

11. The system of claim 10 , wherein the mapping of the first translation table entry to the first dump unit is based on a hash function, the mapping of the first translation table entry to the first dump unit being a hash of a logical block number of the logical block of the first translation table entry.

12. The system of claim 10 , further comprising:

allocating a space in memory for the array of dump units.

13. The system of claim 10 , wherein mapping includes storing the first translation table entry in the first dump unit.

14. The system of claim 10 , further comprising:

storing the first translation table entry in a logical space in memory.

15. The system of claim 10 , wherein the linked list includes updates to the logical block in a reverse chronological order, a most recent update being at a front of the linked list.

16. The system of claim 10 , further comprising:

grouping the array of dump units into a plurality of dump groups; and

assigning a fixed range of logical space in memory to each dump group in the plurality of dump groups.

17. The system of claim 10 , further comprising:

receiving a write request for the logical block, the write request including a new translation table entry for the logical block;

identifying the first dump unit associated with the logical block;

updating the second translation table entry in the storage device with the first translation table entry from the first dump unit;

storing the new translation table entry in the first dump unit; and

updating the linked list in the storage device, the linked list referencing the first translation table entry in the storage device through previous translation table entries associated with the logical block.

18. The system of claim 10 , further comprising:

eliminating duplicate entries for the logical block to get a consolidated representation of translation table entries on the storage device.

19. A computer program product comprising a non-transitory computer usable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer to:

receive a first translation table entry for a logical block;

map the first translation table entry to a first dump unit, the first dump unit included in an array of dump units;

identify a second translation table entry for the logical block in the first dump unit, the second translation table entry also being stored in a storage device; and

generate a linked list in the storage device from the second translation table entry associated with the first dump unit, the linked list identifying previous translation table entries associated with the logical block.

20. The computer program product of claim 19 , wherein mapping includes storing the first translation table entry in the first dump unit.

21. The computer program product of claim 19 , wherein the linked list includes updates to the logical block in a reverse chronological order, a most recent update being at a front of the linked list.

22. The computer program product of claim 19 , further comprising:

grouping the array of dump units into a plurality of dump groups; and

assigning a fixed range of logical space in memory to each dump group in the plurality of dump groups.

23. The computer program product of claim 19 , further comprising:

storing the first translation table entry in a logical space in memory.

Assignments (12)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2016
From: BATTAJE, AJITH KUMAR; GOEL, TANAY; SHARMA, SANDEEP; MANCHANDA, SAURABH; MEDAPATI, ARUN KUMAR
To: HGST NETHERLANDS B.V.
Reel/Frame 039125/0899 →
Continuity (1)
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