Read and write performance for non-volatile memory
View Patent ↗In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
1. A method of matching a memory capacity utilization rate to a memory capacity reclamation rate for a non-volatile memory system, the method comprising:
a) associating a predetermined number of capacity credits in a credit pool with a total memory capacity of the non-volatile memory system;
b) requesting a first number of capacity credits proportional to an amount of memory capacity that is to be consumed by a first write request made by application software or operating system software;
c) blocking the first write request if the first number of capacity credits are unavailable in the credit pool;
d) allocating the first number of capacity credits to the first write request if the first number of capacity credits are available in the credit pool;
e) reducing the number of capacity credits in the credit pool by the first number of capacity credits; and
f) increasing the number of capacity credits in the credit pool by a reclaimed number of capacity credits in proportion to an amount of memory capacity reclaimed by a garbage collection activity, wherein the garbage collection activity can throttle a memory capacity utilization rate in order to match a memory capacity reclamation rate.
2. The method of claim 1 , wherein
the requesting, the blocking, the allocating, the reducing, and the increasing is repeatedly performed to match the memory capacity utilization rate to the memory capacity reclamation rate.
3. The method of claim 2 , wherein
the garbage collection activity continuously adapts the reclaimed number of capacity credits to match the requested number of capacity credits by the application software work load.
4. The method of claim 2 , wherein
the predetermined number of capacity credits in the credit pool is selected between a first threshold and a second threshold to maximize average write performance (e.g., throughput) while minimizing variation in write performance.
5. The method of claim 4 , wherein
the minimizing of the variation of write performance includes
minimizing a number of times the write performance oscillates from above the average write performance to below the average write performance; and
minimizing a difference between minimum write performance and maximum write performance.
6. The method of claim 1 , wherein
one or more of the associating, the requesting, the blocking, the allocating, the reducing, and the increasing is performed with a processor.