Magnetoresistive memory device including a magnetoresistance amplification layer
A magnetoresistive memory cell includes a first electrode, a second electrode that is spaced from the first electrode, a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack containing, from one side to another, a reference layer having a fixed reference magnetization direction, a tunnel barrier layer comprising a dielectric material, and a free layer, and an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.
1. A magnetoresistive memory cell, comprising:
a first electrode;
a second electrode that is spaced from the first electrode;
a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack comprising, from one side to another, a reference layer having a fixed reference magnetization direction; a tunnel barrier layer comprising a dielectric material, and a free layer; and
an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.
2. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer is more proximal to the free layer than to the reference layer.
3. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer is in direct contact with a horizontal surface of the first electrode or the second electrode.
4. The magnetoresistive memory cell of claim 1 , wherein:
the asymmetric magnetoresistance layer is located between the free layer and the second electrode;
the asymmetric magnetoresistance layer has a greater lateral extent than the magnetic tunnel junction layer stack; and
the second electrode is laterally offset from the magnetic tunnel junction layer stack such that the second electrode does not have an areal overlap with the magnetic tunnel junction layer stack.
5. The magnetoresistive memory cell of claim 4 , further comprising a dielectric capping layer located between the free layer and the asymmetric magnetoresistance layer.
6. The magnetoresistive memory cell of claim 1 , wherein:
the asymmetric magnetoresistance layer has a first layer magnetoresistance when a magnetization of the reference layer and a magnetization of the free layer are in a parallel state;
the asymmetric magnetoresistance layer has a second layer magnetoresistance when the magnetization of the reference layer and the magnetization of the free layer are in an antiparallel state; and
a ratio of the second layer magnetoresistance to the first layer magnetoresistance is at least 1.10.
7. The magnetoresistive memory cell of claim 6 , wherein:
the magnetic tunnel junction layer stack has a first junction magnetoresistance when the magnetization of the reference layer and the magnetization of the free layer are in the parallel state; and
the magnetic tunnel junction layer stack has a second junction magnetoresistance when the magnetization of the reference layer and the magnetization of the free layer are in the antiparallel state; and
the second junction magnetoresistance is higher than the first junction magnetoresistance.
8. The magnetoresistive memory cell of claim 7 , wherein the ratio of the second layer magnetoresistance to the first layer magnetoresistance is greater than the ratio of the second junction magnetoresistance to the first junction magnetoresistance.
9. The magnetoresistive memory cell of claim 6 , wherein magnetroresistive memory cell utilizes a stray field of the free layer coupled to the asymmetric magnetoresistance layer to amplify a difference in read current between the parallel state and the antiparallel state.
10. The magnetoresistive memory cell of claim 9 , wherein the asymmetric magnetoresistance layer is non-magnetic.
11. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer overlies the magnetic tunnel junction layer stack and contacts a bottom surface of the second electrode.
12. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer overlies the magnetic tunnel junction layer stack and contacts a top surface of the second electrode.
13. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer underlies the magnetic tunnel junction layer stack and contacts a top surface of the first electrode.
14. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer underlies the magnetic tunnel junction layer stack and contacts a bottom surface of the first electrode.
15. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer comprises a two-dimensional material.
16. The magnetoresistive memory cell of claim 15 , wherein the two-dimensional material is selected from a transition-metal dichalcogenide monolayer, a monolayer graphene, multilayer graphene, or a gapped bilayer graphene.
17. The magnetoresistive memory cell of claim 1 , wherein the asymmetric magnetoresistance layer comprises a topological insulator material having an insulating interior portion and having surfaces containing conducting states.
18. A method of reading the magnetoresistive memory cell of claim 1 , comprising:
applying a read voltage between the first electrode and the second electrode; and
detecting a read current flowing through the magnetic tunnel junction layer stack between the first electrode and the second electrode,
wherein:
the asymmetric magnetoresistance layer has a first layer magnetoresistance when a magnetization of the reference layer and a magnetization of the free layer are in a parallel state;
the asymmetric magnetoresistance layer has a second layer magnetoresistance when the magnetization of the reference layer and the magnetization of the free layer are in an antiparallel state;
a ratio of the second layer magnetoresistance to the first layer magnetoresistance is at least 1.10; and
the magnetroresistive memory cell utilizes a stray field of the free layer coupled to the asymmetric magnetoresistance layer to amplify a difference in the read current between the parallel state and the antiparallel state.
19. A memory device, comprising:
a first metal line laterally extending along a first direction;
a second metal line laterally extending along a second direction; and
the magnetoresistive memory cell of claim 1 located at a cross-point of the first metal line and the second metal line.
20. The memory device of claim 19 , wherein:
the first electrode comprises a portion of the first metal line; and
the second electrode comprises a portion of a second metal line.