IP Library Granted Patent US 10,372,627
Granted Patent B2
US 10,372,627 · App. 15/704,866 · Granted Aug 6, 2019

Method to generate pattern data over garbage data when encryption parameters are changed

Inventors: William Jared Walker (Rochester, MN); Cory Lappi (Rochester, MN); Darin Edward Gerhart (Oronoco, MN); Daniel Robert Lipps (Kasson, MN)
Assignee: Western Digital Technologies, Inc.
G06F12/1408G06F12/1416G06F21/00G06F21/602G06F21/6227G06F21/805G09C1/00H04L9/0891H04L9/0894G06F2221/2123G06F2221/2143H04L2209/12H04L2209/34
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Quick Facts
Patent No.
US 10,372,627
App. No.
15/704,866
Granted
Aug 6, 2019
Kind
B2
Abstract

A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written is disclosed. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of a predefined or custom code is returned in response to an indication of another encryption/decryption method.

Claims (63)

1. A system, comprising:

an arrangement configured with:

at least one physical memory location comprising at least one physical block address configured to store information representing data written using a first encryption/decryption method, wherein the information representing data is in a block; and

a read channel configured to read and decrypt information using a second encryption/decryption method;

an apparatus configured to, in response to an indication that the information was written to the at least one physical memory location using the first encryption/decryption method, prevent the read channel from reading the at least one physical memory location using the second encryption/decryption method by at least: associating a flag with the at least one physical memory location; and returning predefined or custom code for the at least one physical memory location in response to the read channel using the second encryption/decryption method, wherein the apparatus includes a device for writing a predefined or custom code to the at least one physical memory location written in response to the read channel using the second encryption/decryption method; and

an indirection system comprising:

at least one logical block address;

a database configured to map the at least one logical block address to the at least one physical block address; and

an apparatus configured to indicate the at least one logical block address inaccessible in response to the read channel using the second encryption/decryption method.

2. The system of claim 1 , wherein a second encryption parameter associated with the second encryption/decryption method differs from a first encryption parameter associated with the first encryption/decryption method.

3. The system of claim 1 , wherein a second encryption range parameter associated with the second encryption/decryption method differs from a first encryption range parameter associated with the first encryption/decryption method.

4. The system of claim 1 , wherein a second encryption key parameter of the second encryption/decryption method differs from a first encryption key parameter of the first encryption/decryption method.

5. The system of claim 1 , wherein the apparatus configured to prevent the reading of the at least one memory location comprises a device configured to:

associate a flag with the at least one memory location; and

return predefined pattern content for the at least one memory location in response to the read channel using the second encryption/decryption method.

6. The system of claim 1 , wherein the database includes at least one flag indicating an encryption/decryption method used to write and read data from the physical block address.

7. A memory device, comprising:

at least one physical memory location comprising at least one physical block address configured to store information representing data written using a first encryption/decryption method, wherein the information representing data is in a block;

a read channel configured to read and decrypt information using a second encryption/decryption method;

an apparatus configured to, in response to an indication that the information was written to the at least one physical memory location using the first encryption/decryption method, prevent the read channel from reading the at least one physical memory location using the second encryption/decryption method by at least: associating a flag with the at least one physical memory location; and returning predefined or customer code for the at least one physical memory location in response to the read channel using the second encryption/decryption method, wherein the apparatus includes a device for writing a predefined or custom code to the at least one physical memory location written in response to the read channel using the second encryption/decryption method; and

an indirection system comprising:

at least one logical block address;

a database configured to map the at least one logical block address to the at least one physical block address; and

an apparatus configured to indicate the at least one logical block address inaccessible in response to the read channel using the second encryption/decryption method wherein the database includes at least one flag indicating an encryption/decryption method used to write and read data from the physical block address wherein the apparatus is configured to the at least one logical block address inaccessible when the at least one physical block address is written using the first encryption/decryption method, the first encryption/decryption method being different from the second encryption/decryption method.

8. A memory device, comprising:

at least one memory location configured to store information representing data written using a first encryption/decryption method;

a read channel configured to read and decrypt information using a second encryption/decryption technique connected to the at least one memory location; and

an apparatus configured to, in response to an indication that the information was written to the at least one memory location using the first encryption/decryption method, prevent the read channel from reading the at least one memory location using the second encryption/decryption method, wherein the apparatus includes a device for writing a predefined or custom code to the at least one memory location written in response to the read channel using the second encryption/decryption method.

9. The memory device of claim 8 , wherein the apparatus configured to prevent the reading of the at least one memory location comprises a device configured to:

associate a flag with the at least one memory location; and

return predefined pattern content for the at least one memory location in response to the read channel using the second encryption/decryption method.

10. The memory device of claim 8 , wherein the information representing data is in a block and the at least one memory location is at least one physical block address.

11. The memory device of claim 10 , further comprising an indirection system that comprises:

at least one logical block address; and

a database configured to map the at least one logical block address to the at least one physical block address.

12. The memory device of claim 11 , wherein the indirection system further comprises an apparatus configured to indicate the at least one logical block address inaccessible in response to the read channel using the second encryption/decryption method.

13. The memory device of claim 12 , wherein a second encryption parameter associated with the second encryption/decryption method differs from a first encryption parameter associated with the first encryption/decryption method.

14. The memory device of claim 11 , wherein a second encryption range parameter associated with the second encryption/decryption method differs from a first encryption range parameter associated with the first encryption/decryption method.

15. The memory device of claim 11 , wherein a second encryption key parameter of the second encryption/decryption method differs from a first encryption key parameter of the first encryption/decryption method.

16. A storage apparatus, comprising:

a storage medium including a plurality of memory locations;

a write channel connected to the storage medium and configured to write information representing data to the plurality of memory locations;

a read channel connected to the storage medium configured to read information representing data from the plurality of memory locations;

a controller connected to the storage medium, the read channel and the write channel and configured to:

control the write channel to write information to the plurality of memory locations;

control the read channel to read information representing data from the plurality of memory locations;

in response to an indication that the write channel wrote information to at least one memory location of the plurality of memory locations using a first encryption/decryption method, prevent the read channel from reading the at least one memory location using a second, different encryption/decryption method; and

cause the write channel to write the respective physical block address with a predefined or custom code in response to a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

17. The storage apparatus of claim 16 , wherein the controller is further configured to return all the predefined or custom code in response to receiving an indication of a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

18. The storage apparatus of claim 16 , wherein the controller is further configured to remove a pointer in the map between the respective logical block address and the respective physical block address in response to an indication of a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

19. The storage apparatus of claim 16 , wherein the controller is configured to generate a flag indicating information at a respective physical block address is invalid in response to an indication of a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

20. A storage apparatus, comprising:

a storage medium including a plurality of memory locations;

a write channel configured to write information representing data to the plurality of memory locations;

a read channel configured to read information representing data from the plurality of memory locations;

a controller configured to:

control the write channel to write information to the plurality of memory locations;

control the read channel to read information representing data from the plurality of memory locations;

in response to an indication that the write channel wrote information to at least one memory location of the plurality of memory locations using a first encryption/decryption method, prevent the read channel from reading the at least one memory location using a second, different encryption/decryption method; and

cause the write channel to write the respective physical block address with a predefined or custom code in response to a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method;

a set of logical block addresses;

a set of physical block address that correspond to the plurality of physical memory locations in the solid state device of the storage apparatus; and

a map that associates a logical block addresses to at least one physical block address, the map also including at least one flag indicating an encryption/decryption method used to write and read data from the physical block address, wherein the controller returns a reading of a predefined or custom code when the encryption/decryption method used to read the physical block address has changed and renders the physical block address inaccessible when the encryption/decryption method used to read the physical block address is different from the encryption/decryption method used to write the physical block address.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2017
From: WALKER, WILLIAM JARED; LAPPI, CORY; GERHART, DARIN EDWARD; LIPPS, DANIEL ROBERT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043913/0550 →
Continuity (4)
Continuation In Part 15226639 · Aug 2, 2016
Continuation 15051539 · Feb 23, 2016
Continuation 14467724 · Aug 25, 2014
Related Publication 20180018287A1 · Jan 18, 2018