IP Library Granted Patent US 9,959,218
Granted Patent B2
US 9,959,218 · App. 15/226,639 · Granted May 1, 2018

Method and apparatus to generate zero content over garbage data when encryption parameters are changed

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Quick Facts
Patent No.
US 9,959,218
App. No.
15/226,639
Granted
May 1, 2018
Kind
B2
Abstract

A memory device including at least one memory location for storing information representing data written using a first encryption/decryption method, and a read channel using a second encryption/decryption method for reading and decrypting information as written. The memory device also includes an apparatus that prevents the reading of the at least one memory location using the second encryption/decryption method, in response to an indication that the at least one memory location was written using the first encryption/decryption method. In another embodiment, a reading of all zeroes is returned in response to an indication of another encryption/decryption method.

Claims (33)

1. A memory device comprising:

at least one memory location configured to store information representing data written using a first encryption/decryption method, wherein the information representing data is in a block;

a read channel configured to read and decrypt information using a second encryption/decryption technique;

an apparatus configured to, in response to an encryption indication that the information was written to the at least one memory location using the first encryption/decryption method:

generate a flag indicating information at a respective physical block address is invalid in response to an invalidity indication of a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method; and

prevent the read channel from reading the at least one memory location using the second encryption/decryption method by associating the flag with the at least one memory location and by returning zero content for the at least one memory location in response to the read channel using the second encryption/decryption method, wherein the at least one memory location is at least one physical block address; and

an indirection system that comprises: at least one logical block address; and a database configured to map the at least one logical block address to the at least one physical block address.

2. The memory device of claim 1 , wherein the apparatus configured to prevent the reading of the at least one memory location comprises a device for writing zeroes to the at least one memory location written in response to the read channel using the second encryption/decryption method.

3. The memory device of claim 1 , wherein the indirection system further comprises an apparatus configured to indicate the at least one logical block address inaccessible in response to the read channel using the second encryption/decryption method.

4. The memory device of claim 3 , wherein a second encryption parameter associated with the second encryption/decryption method differs from a first encryption parameter associated with the first encryption/decryption method.

5. The memory device of claim 3 , wherein a second encryption range parameter associated with the second encryption/decryption method differs from a first encryption range parameter associated with the first encryption/decryption method.

6. The memory device of claim 3 , wherein a second encryption key parameter of the second encryption/decryption method differs from a first encryption key parameter of the first encryption/decryption method.

7. A storage apparatus comprising:

a storage medium including a plurality of memory locations;

a write channel configured to write information representing data to the plurality of memory locations;

a read channel configured to read information representing data from the plurality of memory locations; and

a controller configured to:

control the write channel to write information to the plurality of memory locations;

control the read channel to read information representing data from the plurality of memory locations;

in response to an encryption indication that the write channel wrote information to at least one memory location of the plurality of memory locations using a first encryption/decryption method, generate a flag in a map between the a respective logical block address and a respective physical block address, wherein the flag indicates information at the respective physical block address is invalid in response to an invalidity indication of a change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method;

prevent the read channel from reading the at least one memory location using a second, different encryption/decryption method; and

cause the write channel to write the respective physical block address with zeroes in response to the change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

8. The storage apparatus of claim 7 , wherein the controller is further configured to return all zeroes in response to receiving the invalidity indication of the change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

9. The storage apparatus of claim 7 , wherein the controller is further configured to remove a pointer in the map between the respective logical block address and the respective physical block address in response to the invalidity indication of the change in the encryption/decryption method from the first encryption/decryption method to the second, different encryption/decryption method.

10. A method comprising:

detecting, by a controller of a storage apparatus, a change in an encryption/decryption scheme used to read and write data to a storage medium;

in response to detecting the change in encryption/decryption scheme, causing, by the controller, a logical block address to return an indication of being written in zeroes when a physical block address associated with the logical block address had been encrypted using an old encryption/decryption scheme; and

causing, by the controller, a write channel to write zeroes using a new encryption/decryption scheme to the physical block address,

wherein respective logical block addresses of a plurality of logical block addresses are associated with respective physical block addresses of a plurality of physical block addresses written with an old encryption/decryption scheme,

wherein the plurality of logical block addresses mapped to the physical block addresses in a map; and

wherein the map comprises at least one flag indicating that information representing data at a respective logical block address is invalid when the information representing data written to the respective physical block address associated with the respective logical block address is written using the old encryption/decryption scheme.

11. The method of claim 10 , further comprising: mapping, by the controller, the logical block address to the physical block address using the map; and removing, by the controller, a pointer from the logical block address to the physical block address in response to detecting the change in encryption/decryption scheme.

12. The method of claim 11 , wherein removing the pointer from the logical block address to the physical block address comprises removing, by the controller, pointers for the plurality of logical block addresses.

Assignments (12)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2016
From: GERHART, DARIN EDWARD; LAPPI, CORY; LIPPS, DANIEL ROBERT; WALKER, WILLIAM JARED
To: HGST NETHERLANDS B.V.
Reel/Frame 039319/0819 →