State-by-state program loop delta detection mode for detecting a defective memory array
Apparatuses and techniques are described for detecting a defect in a memory cell array during program operations. A defect can be detected by comparing the programming speed of memory cells connected to different word lines, for one or more programmed data states. The comparison can involve adjacent word lines in a block, or word lines in different blocks and planes. The comparison involves comparing two word lines in terms of a number of program-verify loops used to reach the programmed data states or to transition between programmed data states. If a program loop delta is not within an allowable range for one or more of the programmed data states, it can be concluded that a defect is present. The block which has the slower programming word line can be identified as a bad block.
1. An apparatus, comprising:
a control circuit configured to connect to a set of memory cells and program the set of memory cells to a plurality of programmed data states, the set of memory cells comprise memory cells connected to a first word line and memory cells connected to a second word line;
in a program operation involving the first word line, the control circuit is configured to perform a plurality of program-verify loops until the memory cells connected to the first word line are programmed to the plurality of programmed data states;
in a program operation involving the second word line, the control circuit is configured to perform a plurality of program-verify loops until the memory cells connected to the second word line are programmed to the plurality of programmed data states;
for at least two comparison data states of the plurality of programmed data states, the control circuit is configured to determine a first difference between a number of program-verify loops used to program memory cells connected to the first word line to a lockout condition of the comparison data state and a number of program-verify loops used to program memory cells connected to the second word line to the lockout condition of the comparison data state; and
the control circuit is configured to determine whether a defect is present in the set of memory cells based on whether the first difference exceeds a respective threshold for the at least two comparison data states and the respective threshold is higher for a higher comparison data state than for a lower comparison data state of the at least two comparison data states.
2. The apparatus of claim 1 , wherein:
the control circuit is configured to determine that the defect is present when the first difference exceeds the respective threshold for a single comparison data state of the plurality of programmed data states.
3. The apparatus of claim 1 , wherein:
the set of memory cells further comprise memory cells connected to a third word line;
in a program operation involving the third word line, the control circuit is configured to perform a plurality of program-verify loops until the memory cells connected to the third word line are programmed to the plurality of programmed data states;
for the at least two comparison data states of the plurality of programmed data states, the control circuit is configured to determine a second difference between a number of program-verify loops used to program memory cells connected to the first word line to a lockout condition of the comparison data state and a number of program-verify loops used to program memory cells connected to the third word line to the lockout condition of the comparison data state.
4. The apparatus of claim 3 , wherein:
the first word line and the second word line are in a first block; and
the third word line is in a second block.
5. The apparatus of claim 1 , wherein:
the at least two comparison data states are in an upper half of the plurality of programmed data states.
6. The apparatus of claim 1 , wherein:
the first word line and the second word line are adjacent in a block.
7. The apparatus of claim 1 , wherein:
the first word line and the second word line are separated by no more than three other word lines in a block.
8. The apparatus of claim 1 , wherein: the control circuit is configured to determine that the defect is present when the first difference exceeds the respective threshold for the at least two comparison data states, and when programming of the memory cells connected to the first word line and programming of the memory cells connected to the second word line are completed within an allowable number of program-verify loops.
9. The apparatus of claim 1 , wherein:
the first word line and the second word line are in a first block and a second block, respectively.
10. The apparatus of claim 9 , wherein: the set of memory cells comprise memory cells connected to a third word line; the third word line is in the first block; in a program operation involving the third word line, the control circuit is configured to perform a plurality of program-verify loops until the memory cells connected to the third word line are programmed to the plurality of programmed data states; for the at least two comparison data states of the plurality of programmed data states, the control circuit is configured to determine a second difference between a number of program-verify loops used to program memory cells connected to the first word line to the comparison data state, and a number of program-verify loops used to program memory cells connected to the third word line to the comparison data state; and the control circuit is configured to determine whether the defect is present based on whether the second difference exceeds a respective threshold for the at least two comparison data states.
11. A method, comprising: performing a plurality of program-verify loops for memory cells connected to a first word line until the memory cells connected to the first word line are programmed to a plurality of programmed data states; performing a plurality of program-verify loops for memory cells connected to a second word line until the memory cells connected to the second word line are programmed to the plurality of programmed data states; for a first comparison data state in an upper half of the plurality of programmed data states, determining a first difference between a number of program-verify loops used to program the memory cells connected to the first word line to a lockout condition of the first comparison data state and a number of program-verify loops used to program the memory cells connected to the second word line to the lockout condition of the first comparison data state; for a second comparison data state in the upper half of the plurality of programmed data states, determining a second difference between a number of program-verify loops used to program the memory cells connected to the first word line to the second comparison data state and a number of program-verify loops used to program memory cells connected to the second word line to the second comparison data state; and determining whether a defect is present based on whether the first difference and the second difference exceeds respective thresholds for the first comparison data state and the second comparison data state.
12. The method of claim 11 , wherein:
determining whether the defect is present includes comparing the first difference with a first threshold for the first comparison data state and comparing the second difference with a second threshold for the second comparison data state.
13. The method of claim 11 , wherein:
the respective threshold for the first comparison data state is different than the respective threshold for the second comparison data state.
14. The method of claim 12 , wherein:
the first comparison data state is higher than the second comparison data state and the first threshold is higher than the second threshold.
15. The method of claim 11 , wherein:
the first word line and the second word line are adjacent in a block.
16. An apparatus, comprising:
a control circuit configured to connect to a set of memory cells, the set of memory cells comprise memory cells connected to a first word line and memory cells connected to a second word line; and
an interface connected to the control circuit, the control circuit is configured to issue commands via the interface to:
perform a program operation comprising a plurality of program-verify loops for the memory cells connected to the first word line;
determine a first number of program-verify loops used to transition the memory cells connected to the first word line between two data states that are in an upper half of a plurality of programmed data states, the first number of program-verify loops is a difference between a program-verify loop in which programming is completed for a first data state of the two data states and a program-verify loop in which programming is completed for a second data state of the two data states;
perform a program operation comprising a plurality of program-verify loops for the memory cells connected to the second word line;
determine a second number of program-verify loops used to transition the memory cells connected to the second word line between the two data states, the second number of program-verify loops is a difference between a program-verify loop in which programming is completed for the first data state of the two data states and a program-verify loop in which programming is completed for the second data state of the two data states; and
determine whether a difference between the first number and the second number is within an allowable range.
17. The apparatus of claim 16 , wherein:
the first word line and the second word line are in a block; and
the control circuit is configured to identify the block as being defective if the difference between the first number and the second number is not within the allowable range.
18. The apparatus of claim 16 , wherein:
the first word line is in a first block;
the second word line is in a second block; and
the control circuit is configured to identify the first block as being defective if the difference between the first number and the second number is not within the allowable range, and the first number exceeds the second number.
19. The apparatus of claim 16 , wherein:
the memory cells connected to the first word line are programmed to the plurality of programmed data states in the program operation for the memory cells connected to the first word line;
the memory cells connected to the second word line are programmed to the plurality of programmed data states in the program operation for the memory cells connected to the second word line; and
the two data states are programmed data states among the plurality of programmed data states.
20. The apparatus of claim 16 , wherein:
the first word line is in a first block;
the second word line is in a second block;
the set of memory cells further comprise memory cells connected to a third word line that is located in the first block;
in the program operation, the control circuit is further configured to issue commands via the interface to perform a plurality of program-verify loops until the memory cells connected to the third word line are programmed to the plurality of programmed data states;
determine a third number of program-verify loops used to transition the memory cells connected to the third word line between the two data states, the third number of program-verify loops is a difference between a program-verify loop in which programming is completed for the first data state of the two data states and a program-verify loop in which programming is completed for the second data state of the two data states.