Multi-rate ECC parity for fast SLC read
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
create a dual parity construction matrix, wherein the dual parity construction matrix comprises:
a full parity form that includes a payload, a first parity portion, and a second parity portion, wherein the full parity form includes the payload arranged in a first half and a second half, wherein the first half comprises half of the payload, wherein the second half comprises another half of the payload, and wherein the first half and the second half are disjointed; and
a reduced parity form that includes the payload and the first parity portion, wherein the second parity portion is 0;
receive a read request for data associated with the dual parity construction matrix;
determine that the read request is a single level cell (SLC) read request; and
transfer and decode the data using reduced parity.
2. The data storage device of claim 1 , wherein the full parity form includes the second parity portion arranged in a first half and a second half, wherein the first half comprises an entirety of the second parity portion, wherein the second half comprises the entirety of the second parity portion.
3. The data storage device of claim 1 , wherein the full parity form is divided into two arrays, wherein a first array of the two arrays comprises:
a first half of the payload;
a first half of the first parity portion; and
the second parity portion.
4. The data storage device of claim 3 , wherein a second array of the two arrays comprises:
a second half of the payload;
a second half of the first parity portion; and
the second parity portion.
5. The data storage device of claim 4 , wherein the reduced parity comprises:
the first half of the payload added to the second half of the payload;
the first half of the first parity portion added to the second half of the first parity portion; and
a value of 0 for the second parity portion.
6. The data storage device of claim 5 , wherein the first half of the payload added to the second half of the payload is non zero.
7. The data storage device of claim 5 , wherein the first half of the first parity portion added to the second half of the first parity portion is non zero.
8. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
create a dual parity construction matrix, wherein the dual parity construction matrix comprises:
a full parity form that includes a payload, a first parity portion, and a second parity portion, wherein the full parity form includes the first parity portion arranged in a first half and a second half, wherein the first half comprises half of the first parity portion, wherein the second half comprises another half of the first parity portion, and wherein the first half and the second half are disjointed; and
a reduced parity form that includes the payload and the first parity portion, wherein the second parity portion is 0;
receive a read request for data associated with the dual parity construction matrix;
determine that the read request is a single level cell (SLC) read request; and
transfer and decode the data using reduced parity.
9. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
encode data using an encoding matrix, wherein the encoding matrix comprises:
a dual parity construction comprising:
a full parity form, wherein the full parity form is arranged in two arrays, wherein:
a first array of the two arrays comprises:
a first payload portion;
a first, first parity portion; and
a first, second parity portion;
a second array of the two arrays comprises:
a second payload portion;
a second, first party portion; and
a second, second parity portion; and
the first payload portion and the second payload portion each comprises non-zero elements and are disjointed; and
a reduced parity form, wherein the reduced parity form is arranged in a single array, wherein the single array comprises:
a payload portion comprising the first payload portion added to the second payload portion;
a first parity portion comprising the first, first parity portion added to the second, first parity portion; and
a second parity portion comprising the first, second parity portion added to the second, second parity portion, wherein at least one of the first parity portion and the second parity portion is 0;
program the data to the memory means;
receive a read request to read the data;
determine that the read request is a single level cell (SLC) read request; and
transfer and decode the data using reduced parity.
10. The data storage device of claim 9 , wherein the controller is further configured to transfer and decode the data using full parity upon determining the reduced parity decoding failed.