Granted Patent B2

US 10,235,069 · App. 15/388,768 · Granted Mar 19, 2019

Inventors: Adam Michael Espeseth (Rochester, MN); Brent William Jacobs (Rochester, MN)

Assignee: Western Digital Technologies, Inc.

G06F3/0622G06F3/0659G06F3/0679G06F3/0688G06F12/0246G06F12/1009G06F2212/2022G06F2212/7201G06F2212/7205

Abstract

Claims (85)

1. A method for accessing a storage device, comprising:

receiving, from a host apparatus, an access request directed at two or more storage addresses;

assigning, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device;

obtaining a local memory lock based on the first storage address;

determining, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors;

obtaining a remote memory lock from the second processor based on the second storage address;

issuing a transition barrier command to each processor of the two or more processors;

receiving, from each processor of the two or more processors, a response to the transition barrier command;

issuing a transition barrier complete message to each processor of the two or more processors after receiving the response from all of the two or more processors; and

processing the access request.

2. The method of claim 1 , further comprising:

determining to change from a first algorithm for assigning storage addresses to the two or more processors to a second algorithm.

3. The method of claim 2 , wherein the transition barrier command includes the second algorithm.

4. The method of claim 2 , further comprising:

determining, for a third storage address, a first assigned processor based on the first algorithm and a second assigned processor based on the second algorithm; and

obtaining memory locks based on both the first and second assigned processors.

5. The method of claim 4 , wherein obtaining memory locks comprises:

determining the first or second assigned processor is different from a current processor; and

obtaining a remote memory lock from the first or second assigned processor based on the determination.

6. The method of claim 4 , wherein obtaining memory locks comprises:

determining the first or second assigned processor is the same as a current processor; and

obtaining a local memory lock based on the determination.

7. The method of claim 2 , wherein the response indicating each processor has finished processing access requests is sent by each processor after each processor has finished processing access requests received prior to the transition barrier command.

8. A computer system for storing and retrieving data, comprising:

a processor; and

a memory storing instructions that, when executed by the processor, cause the computer system to:

receive, from a host apparatus, an access request directed at two or more storage addresses;

assign, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device;

obtain a local memory lock based on the first storage address;

determine, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors;

obtain a remote memory lock from the second processor based on the second storage address;

issue a transition barrier command to each processor of the two or more processors;

receive, from each processor of the two or more processors, a response to the transition barrier command;

issue a transition barrier complete message to each processor of the two or more processors after receiving the response from all of the two or more processors; and

process the access request.

9. The computer system of claim 8 , wherein the instructions cause the computer system to:

determine to change from a first algorithm for assigning storage addresses to the two or more processors to a second algorithm.

10. The computer system of claim 9 , wherein the transition barrier command includes the second algorithm.

11. The computer system of claim 9 , wherein the instructions cause the computer system to:

determine, for a third storage address, a first assigned processor based on the first algorithm and a second assigned processor based on the second algorithm; and

obtain memory locks based on both the first and second assigned processors.

12. The computer system of claim 11 , wherein obtain memory locks comprises:

determining the first or second assigned processor is different from a current processor; and

obtaining a remote memory lock from the first or second assigned processor based on the determination.

13. The computer system of claim 11 , wherein obtain memory locks comprises:

determining the first or second assigned processor is the same as a current processor; and

obtaining a local memory lock based on the determination.

14. The computer system of claim 9 , wherein the response indicating each processor has finished processing access requests is sent by each processor after each processor has finished processing access requests received prior to the transition barrier command.

15. A non-transitory computer readable storage medium containing instructions that, when executed by a processor, performs the following method:

receive, from a host apparatus, an access request directed at two or more storage addresses;

assign, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device;

obtain a local memory lock based on the first storage address;

determine, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors;

obtain a remote memory lock from the second processor based on the second storage address;

issue a transition barrier command to each processor of the two or more processors;

receive, from each processor of the two or more processors, a response to the transition barrier command;

issue a transition barrier complete message to each processor of the two or more processors after receiving the response from all of the two or more processors; and

process the access request.

16. The non-transitory computer readable storage medium of claim 15 , wherein the instructions cause the computer system to:

determine to change from a first algorithm for assigning storage addresses to the two or more processors to a second algorithm.

17. The non-transitory computer readable storage medium of claim 16 , wherein the transition barrier command includes the second algorithm.

18. The non-transitory computer readable storage medium of claim 16 , wherein the instructions cause the computer system to:

determine, for a third storage address, a first assigned processor based on the first algorithm and a second assigned processor based on the second algorithm; and

obtain memory locks based on both the first and second assigned processors.

19. The non-transitory computer readable storage medium of claim 18 , wherein obtain memory locks comprises:

determining the first or second assigned processor is different from a current processor; and

obtaining a remote memory lock from the first or second assigned processor based on the determination.

20. The non-transitory computer readable storage medium of claim 18 , wherein obtain memory locks comprises:

determining the first or second assigned processor is the same as a current processor; and

obtaining a local memory lock based on the determination.

21. The non-transitory computer readable storage medium of claim 16 , wherein the response indicating each processor has finished processing access requests is sent by each processor after each processor has finished processing access requests received prior to the transition barrier command.

22. A device, comprising:

means for receiving, from a host apparatus, an access request directed at two or more storage addresses;

means for assigning, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device;

first means for obtaining a local memory lock based on the first storage address;

means for determining, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors;

second means for obtaining a remote memory lock from the second processor based on the second storage address;

means for issuing a transition barrier command to each processor of the two or more processors;

means for receiving, from each processor of the two or more processors, a response to the transition barrier command;

means for issuing a transition barrier complete message to each processor of the two or more processors after receiving the response from all of the two or more processors; and

means for processing the access request.

23. The device of claim 22 , wherein the first means for obtaining a local memory lock and the second means for obtaining a remote memory lock are the same means.

24. The device of claim 23 , wherein the means for receiving, the means for assigning, the first means for obtaining a local memory lock, the means for determining and the second means for obtaining a remote memory lock are the same means.

25. The device of claim 22 , wherein the means for processing comprises a plurality of means for processing.

26. The device of claim 25 , further comprising means for indicating each means for processing has finished processing access requests.

Assignments (10)

Continuity (1)