IP Library Granted Patent US 12,067,289
Granted Patent B2
US 12,067,289 · App. 17/571,841 · Granted Aug 20, 2024

Data storage device and method for memory-die-state-aware host command submission

Inventors: Amit Sharma (Bengaluru, IN); Dinesh Kumar Agarwal (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 12,067,289
App. No.
17/571,841
Granted
Aug 20, 2024
Kind
B2
Abstract

A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is configured to receive a query from a host for a status of a memory die that will be accessed by a command; determine the status of the memory die; and respond to the query by providing the status of the memory die to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Claims (30)

1. A data storage device comprising:

a memory comprising a plurality of memory dies; and a controller configured to: receive a request from a host for a storage location of a logical-to-physical address translation map that includes a memory die ready/busy status for each physical address in the logical-to-physical address translation map, wherein a busy status for one of the plurality of memory dies indicates that the one of the plurality of memory dies is busy with an ongoing memory operation and that a new memory operation to the memory die will be delayed until after the ongoing memory operation is completed;

respond to the request by providing the storage location of the logical-to-physical address translation map to the host; and

receive a command from the host to perform a memory operation on a logical address that translates, in the logical-to-physical address translation map, to a physical address in one of the plurality of memory dies that is indicated to be ready, wherein the command is selected by the host after the host accesses the logical-to-physical address translation map at the storage location to determine that the one of the plurality of memory dies is indicated to be ready.

2. The data storage device of claim 1 , wherein the request alone does not cause the command to be placed in a command queue in the data storage device for execution.

3. The data storage device of claim 1 , wherein the controller is further configured to receive a second request from the host for the storage location of the logical-to-physical address translation map.

4. The data storage device of claim 1 , wherein the controller is further configured to receive the request in a vendor-specific command.

5. The data storage device of claim 1 , wherein the plurality of memory dies is configured with processing capabilities.

6. The data storage device of claim 1 , wherein the controller is further configured to reorder pending operations in the data storage device.

7. The data storage device of claim 1 , wherein the controller is further configured to split a single command into multiple commands.

8. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

9. A method comprising:

performing the following in a host in communication with a data storage device comprising a memory comprising a plurality of memory dies:

sending a request to the data storage device for a storage location of a logical-to-physical address translation map that includes a memory die ready/busy status for each physical address in the logical-to-physical address translation map, wherein a busy status for one of the plurality of memory dies indicates that the one of the plurality of memory dies is busy with an ongoing memory operation and that a new memory operation to the memory die will be delayed until after the ongoing memory operation is completed;

accessing the logical-to-physical address translation map;

selecting, from a plurality of commands, a command comprising a logical address that translates, in the logical-to-physical address translation map, to a physical address in one of the plurality of memory dies that is indicated to be ready; and

sending the command to the data storage device.

10. The method of claim 9 , wherein the storage location is in a host memory buffer in the host.

11. The method of claim 9 , wherein the storage location is in a controller memory buffer in the data storage device.

12. The method of claim 9 , wherein the request is sent in a vendor-specific command.

13. The method of claim 9 , further comprising, prior to sending the request, inquiring whether the data storage device is configured to share the logical-to-physical address translation map.

14. The method of claim 9 , further comprising reordering pending operations in the data storage device.

15. The method of claim 9 , further comprising splitting a single command into multiple commands.

16. The method of claim 9 , further comprising negotiating the storage location with the data storage device.

17. The method of claim 9 , wherein the plurality of memory dies is configured with processing capabilities.

18. The method of claim 9 , wherein the plurality of commands comprises read commands and/or write commands.

19. A data storage device comprising:

a memory comprising a plurality of memory dies;

means for providing a host with a storage location of a logical-to-physical address translation map that includes a memory die ready/busy status for each physical address in the logical-to-physical address translation map, wherein a busy status for one of the plurality of memory dies indicates that the one of the plurality of memory dies is busy with an ongoing memory operation and that a new memory operation to the memory die will be delayed until after the ongoing memory operation is completed; and

means for receiving a command from the host to perform a memory operation on a logical address that translates, in the logical-to-physical address translation map, to a physical address in one of the plurality of memory dies that is indicated to be ready, wherein the command is selected by the host after the host accesses the logical-to-physical address translation map at the storage location to determine that the one of the plurality of memory dies is indicated to be ready.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2022
From: SHARMA, AMIT; AGARWAL, DINESH KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058609/0953 →
Continuity (1)
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