Granted Patent B2

US 9,223,373 · App. 13/842,101 · Granted Dec 29, 2015

Abstract

Claims (43)

1. A storage device, comprising:

a flash memory;

a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory; and

a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to

receive a plurality of power requests via one or more of the plurality of flash channels,

receive a power budget from the controller, and

process the plurality of power requests based on the power budget and a respective priority identifier associated with each of the plurality of power requests.

2. The storage device of claim 1 , wherein the power arbiter unit is further configured to perform operations for:

providing power to the flash memory via one or more of the plurality of flash channels based on a power weight identifier associated with the one or more of the plurality of power requests.

3. The storage device of claim 1 , wherein the power arbiter unit further comprises:

a channel queue comprising a plurality of channel FIFOs; and

a priority queue comprising a plurality of priority FIFOs,

wherein the power arbiter unit is further configured to perform operations for:

storing the plurality of power requests in one or more of the channel FIFOs; and

transferring one or more of the plurality of power requests from the one or more of the channel FIFOs to one or more of the priority FIFOs based on the priority identifier associated with the one or more of the plurality of power requests.

4. The storage device of claim 3 , wherein the power arbiter unit is further configured to perform operations comprising:

processing the one or more of the plurality of power requests based on a priority designation associated with the one or more of the priority FIFOs.

5. The storage device of claim 3 , wherein the power arbiter unit is further configured to perform operations for:

transferring at least one of the plurality of power requests from a first priority FIFO to a second priority FIFO from among priority FIFOs.

6. A computer-implemented method, comprising:

receiving, at a power arbiter unit, a plurality of power requests from a flash memory via one or more of a plurality of flash channels;

receiving a power budget from a controller; and

processing one or more of the plurality of power requests based on the power budget and a priority identifier associated with the one or more of the plurality of power requests.

7. The computer-implemented method of claim 6 , wherein processing the one or more of the plurality of power requests further comprises:

providing power to the flash memory via the one or more of the plurality of flash channels based on a power weight identifier associated with the one or more of the plurality of power requests.

8. The computer-implemented method of claim 6 , further comprising:

storing the plurality of power requests in one or more of channel FIFOs; and

transferring the one or more of the plurality of power requests from one or more channel FIFOs, from among a plurality of channel FIFOs, to one or more priority FIFOs, from among a plurality of priority FIFOs, based on the priority identifier associated with the one or more of the plurality of power requests.

9. The computer-implemented method of claim 8 , wherein processing the one or more of the plurality of power requests is performed based on a priority designation associated with the one or more of the priority FIFOs.

10. The computer-implemented method of claim 8 , further comprising:

transferring at least one of the plurality of power requests from a first priority FIFO from among the plurality of priority FIFOs to a second priority FIFO from among the plurality of priority FIFOs.

11. A non-transitory computer-readable storage medium comprising instructions stored therein, which when executed by a processor, cause the processor to perform operations comprising:

receiving, at a power arbiter unit, a plurality of power requests from a flash memory via one or more of a plurality of flash channels;

receiving a power budget from a controller; and

processing one or more of the plurality of power requests based on the power budget and a priority identifier associated with the one or more of the plurality of power requests.

12. The non-transitory computer-readable storage medium of claim 11 , wherein processing the one or more of the plurality of power requests further comprises:

providing power to the flash memory via one or more of the plurality of flash channels based on a power weight identifier associated with the one or more of the plurality of power requests.

13. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions, when executed by the processor, further cause the processor to perform operations comprising:

storing the plurality of power requests in one or more of channel FIFOs; and

transferring the one or more of the plurality of power requests from one or more channel FIFOs, from among a plurality of channel FIFOs, to one or more priority FIFOs, from among a plurality of priority FIFOs, based on the priority identifier associated with the one or more of the plurality of power requests.

14. The non-transitory computer-readable storage medium of claim 13 , wherein processing the one or more of the plurality of power requests is performed based on a priority designation associated with the one or more of the priority FIFOs.

15. The non-transitory computer-readable storage medium of claim 13 , further comprising:

transferring at least one of the plurality of power requests from a first priority FIFO from among the plurality of priority FIFOs to a second priority FIFO from among the plurality of priority FIFOs.

Assignments (12)