Write efficiency in magneto-resistive random access memories
A system and method include determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device. The value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric. The system and method also include writing each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.
1. A method comprising:
determining, by a memory controller associated with a memory device, a value of a parameter of a write pulse for a plurality of bits of a B-bit word to be stored in the memory device, wherein the value of the parameter is based upon a relative importance of a bit position of the plurality of bits in the B-bit word to a performance of a machine learning or signal processing task involving the B-bit word, a fidelity metric, and a resource metric; and
writing, by the memory controller, each of the plurality of bits of the B-bit word in a different sub-array of the memory device using the write pulse generated based on the value of the parameter determined for a particular one of the plurality of bits.
2. The method of claim 1 , wherein the value of the parameter of the write pulse is determined to minimize the fidelity metric while satisfying the resource metric.
3. The method of claim 1 , wherein the parameter of the write pulse comprises at least one of write current, pulse width, or write voltage.
4. The method of claim 1 , further comprising determining, by the memory controller, the value of the parameter of the write pulse to satisfy a granularity.
5. The method of claim 1 , further comprising identifying, by the memory controller, the relative importance of the bit position of each of the plurality of bits before determining the value of the parameter of the write pulse.
6. The method of claim 1 , wherein a most significant bit of the B-bit word has a higher relative importance than that of a least significant bit of the B-bit word.
7. The method of claim 6 , wherein the value of the parameter of the write pulse of the most significant bit is greater than the value of the parameter of the write pulse of the least significant bit.
8. The method of claim 1 , wherein the parameter is write current or pulse width, and wherein the bit position that is of greater relative importance is assigned a greater write current and/or longer pulse width than the bit position that is of lesser relative importance.
9. The method of claim 1 , wherein the memory device comprises a magneto-resistive random access memory device.
10. The method of claim 1 , wherein the fidelity metric comprises at least one of mean square error or peak signal-to-noise ratio.
11. The method of claim 1 , wherein the resource metric comprises write energy.
12. The method of claim 1 , further comprising dynamically updating, by the memory controller, the value of the parameter of the write pulse for the bit position of the plurality of bits upon receiving a new fidelity metric or a new resource metric.
13. The method of claim 1 , wherein determining the value of the parameter of the write pulse comprises inputting the fidelity metric or the resource metric into a look-up table, and receiving the value of the parameter of the write pulse as an output from the look-up table.
14. The method of claim 1 , further comprising performing, by the memory controller, a wear leveling operation in which the sub-array currently designated to store a particular bit position is designated to store a different bit position upon satisfaction of a pre-determined condition.
15. A system comprising:
a memory device comprising a plurality of sub-arrays, wherein each of the plurality of sub-arrays stores one bit of a B-bit word; and
a memory controller in operational association with each of the plurality of sub-arrays, wherein the memory controller comprises programmed instructions to:
determine a first write pulse for a most significant bit of the B-bit word and a second write pulse for a least significant bit of the B-bit word, wherein a value of a parameter of the first write pulse is greater than the value of the parameter of the second write pulse, and wherein the values of the parameter of the first write pulse and the second write pulse are determined to minimize a fidelity metric and satisfy a resource metric, and to reflect a relative importance of the most significant bit and the least significant bit to a performance of a machine learning or signal processing task involving the B-bit word; and
store the most significant bit in a first sub-array of the plurality of sub-arrays based on the first write pulse and store the least significant bit in a second sub-array of the plurality of sub-arrays based on the second write pulse.
16. The system of claim 15 , wherein the memory device comprises a magneto-resistive random access memory.
17. The system of claim 15 , wherein the parameter comprises at least one of write current, pulse width, or write voltage.
18. The system of claim 15 , wherein each of the plurality of sub-arrays is dedicated to storing a designated bit position of the B-bit word.
19. The system of claim 15 , wherein the memory controller further comprises programmed instructions to dynamically update the parameter of the first write pulse and the parameter of the second write pulse upon receiving a new fidelity metric or a new resource metric.
20. A non-transitory computer-readable medium comprising computer-readable instructions stored thereon that when executed by a processor associated with a magneto-resistive random access memory causes the processor to:
receive a fidelity metric, a resource metric, and a granularity; and
determine a value of a parameter of a write pulse for a plurality of bit positions of a B-bit word to satisfy the granularity and the resource metric while minimizing the fidelity metric, and to reflect a relative importance of the plurality of bit positions to a performance of a machine learning or signal processing task involving the B-bit word,
wherein the value of the parameter of the write pulse for a more important bit position is greater than the value of the parameter of the write pulse for a lesser important bit position.
21. The non-transitory computer-readable medium of claim 20 , wherein the more important bit position is a most significant bit, and wherein the lesser important bit position is a least significant bit.
22. The non-transitory computer-readable medium of claim 20 , wherein the parameter comprises at least one of write current, pulse width, or write voltage.
23. The non-transitory computer-readable medium of claim 20 , wherein the processor further comprises instructions to dynamically update the value of the write pulse for the plurality of bit positions upon receiving a new fidelity metric, a new resource metric, or a new granularity.