IP Library Granted Patent US 9,223,702
Granted Patent B2
US 9,223,702 · App. 14/457,077 · Granted Dec 29, 2015

Systems and methods for read caching in flash storage

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Quick Facts
Patent No.
US 9,223,702
App. No.
14/457,077
Granted
Dec 29, 2015
Kind
B2
Abstract

A flash controller receives a read request for reading a page of data from the flash memory from a host system, and identifies, in a cache tag table stored in the random access memory, a virtual unit address associated with the page of data. In response to identifying the virtual unit address in the cache tag table, controller determines whether a valid tag line for the page of data is associated with the virtual unit address in the cache tag table. In response to determining that the valid tag line is associated with the virtual unit address in the cache tag table, the controller reads the page of data from the random access memory in accordance with the read request and returns the read data to the host system.

Claims (54)

1. A method of managing a flash storage device, the method comprising:

receiving a read request for reading a page of data from a non-volatile memory;

identifying, in a cache tag table stored in a cache memory different from the non-volatile memory, a virtual unit address associated with the page of data;

in response to identifying the virtual unit address in the cache tag table, determining whether, in a sub-table of the cache tag table, a valid tag line for the page of data is associated with the virtual unit address, the valid tag line indicating that the page of data includes valid data; and

in response to determining that the valid tag line is associated with the virtual unit address in the cache tag table, reading the page of data from the cache memory in accordance with the read request.

2. The method of claim 1 , wherein the cache tag table comprises a plurality of sub-tables for locating virtual pages stored in the cache memory based on respective virtual page addresses, each sub-table being associated with a respective virtual unit address.

3. The method of claim 1 , wherein the valid tag line is indexed by a virtual page address for the page of data.

4. The method of claim 1 , further comprising, in response to not determining that the valid tag line is associated with the virtual unit address in the cache tag table:

reading the page of data from the non-volatile memory;

storing the page of data in the cache memory; and

associating the valid to line with the virtual unit address in the cache tag table.

5. The method of claim 1 , wherein a maximum number of valid tag lines associated with a respective virtual unit address in the cache tag table is less than a total number of virtual pages in a virtual unit corresponding to the virtual unit address.

6. The method of claim 5 , further comprising:

when the maximum number of valid tag lines are associated with the respective virtual unit address, invalidating one or more of the valid tag lines before associating another valid tag line with the respective virtual unit address.

7. The method of claim 6 , wherein invalidating one or more of the valid tag lines comprises invalidating a tag line associated with a least recently used virtual page address.

8. The method of claim 1 , further comprising:

determining if a valid tag line for a virtual page address associated with a write command is in the cache tag table;

in response to determining the valid tag line for the virtual page address associated with the write command is in the cache tag table, invalidating the valid tag line for the virtual page address.

9. The method of claim 1 , further comprising:

writing one or more new pages of data to the non-volatile memory;

writing the one or more new pages of data to the cache memory; and

associating valid tag lines for the one or more new pages of data with a corresponding virtual unit address in the cache tag table.

10. The method of claim 1 , further comprising:

mapping a host logical address in the read request to the virtual it address and a virtual. page address for the page of data.

11. A system, comprising:

a random access memory;

a flash memory comprising a plurality of physical blocks, each of the plurality of physical blocks comprising a plurality of physical pages;

a controller, wherein the controller is configured to:

receive a read request for reading a page of data from the flash memory;

identify, in a cache tag table stored in the random access memory, a virtual unit address associated with the page of data;

in response to identifying the virtual unit address in the cache tag table, determine whether, in a sub-table of the cache tag table, a valid tag line for the page of data is associated with the virtual unit address, the valid tag line being indexed by a virtual page address for the page of data and indicating that the page of data includes valid data; and

in response to determining that the valid tag line is associated with the virtual unit address in the cache tag table, read the page of data from the random access memory in accordance with the read request.

12. The system of claim lit wherein the cache tag table comprises a plurality of sub-tables for locating virtual pages stored in the random access memory based on respective virtual page addresses, each sub-table being associated with a respective virtual unit address.

13. The system of claim 11 , wherein the controller is further configured to, in response to not determining that the valid tag line is associated with the virtual unit address in the cache tag table:

reading the page of data from the flash memory;

storing the page of data in the random access memory; and

associating the valid tag line with the virtual unit address in the cache tag table.

14. The system of claim 1 , wherein a maximum number of valid tag lines associated with a respective virtual unit address in the cache tag table is less than a total number of virtual pages in a virtual unit corresponding to the virtual unit address.

15. The system of claim 14 , wherein the controller is further configured to:

when the maximum number of valid tag lines are associated with the respective virtual unit address, invalidating one or more of the valid tag lines before associating another valid tag line with the respective virtual unit address.

16. The system of claim 15 , wherein invalidating one or more of the valid tag lines comprises invalidating a tag line associated with a least recently used virtual page address.

17. The system of claim 11 , wherein the controller is further configured to:

determining if a valid tag line for a virtual page address associated with a write command is in the cache tag table;

in response to determining the valid tag line for the virtual page address associated with the write command is in the cache tag table, invalidating the valid tag line for the virtual page address.

18. The system of claim 11 , wherein the controller is further configured to:

writing one or more new pages of data to the flash memory;

writing the one or more new pages of data to the random access memory; and

associating valid tag lines for the one or more new pages of data with a corresponding virtual unit address in the cache tag table.

19. A flash controller, comprising non-transitory instructions stored therein that, when executed by the controller, perform the operations of:

receiving a read request for reading a page of data from a one or more flash memory devices;

identifying, in a cache tag table stored in a cache memory different from the flash memory, a virtual unit address associated with the page of data;

in response to identifying the virtual unit address in the cache tag table, determining whether, in a sub-table of the cache tag table, a valid tag line for the page of data is associated with the virtual unit address, the valid tag line being indexed by a virtual page address for the page of data and indicating that the page of data includes valid data; and

in response to determining that the valid tag line is associated with the virtual unit address in the cache tag table, reading the page of data from the cache memory in accordance with the read request.

20. The flash controller of claim 19 , wherein the cache tag table comprises a plurality of sub-tables for locating virtual pages stored in the cache memory based on respective virtual page addresses, each sub-table being associated with a respective virtual unit address.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY DATA PREVIOUSLY RECORDED AT REEL: 034702 FRAME: 0096. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 24, 2015
From: HSUEH, PO-JEN; MATAYA, RICHARD A.; MOSHAYEDI, MARK
To: STEC, INC.
Reel/Frame 036472/0348 →
CHANGE OF NAME Recorded Aug 24, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036437/0856 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2015
From: HSUEH, PO-JEN; MATAYA, RICHARD A.; MOSHAYEDI, MARK
To: HGST NETHERLANDS B.V.
Reel/Frame 034702/0096 →