IP Library Granted Patent US 11,513,720
Granted Patent B1
US 11,513,720 · App. 17/345,877 · Granted Nov 29, 2022

Data storage device having predictive analytics

Inventors: Shaheed Nehal A (Bangalore, IN); Lovish Singla (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0652G06F3/064G06F3/0604G06F3/0659G06F3/0679G06F12/0253G06N3/0454
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Quick Facts
Patent No.
US 11,513,720
App. No.
17/345,877
Granted
Nov 29, 2022
Kind
B1
Abstract

A method and apparatus for sustaining performance of a data storage device by predictively determining resource needs and executing processes to meet those needs before the resources are actually needed. According to certain embodiments, a controller collects commands coming from a host and provides these to a machine learning model such as a recurrent neural network (RNN). The RNN is trained using this data, and output of the trained model is used to predict future commands. As future commands are developed by the RNN, resource allocation processes such as garbage collection may be initiated prior to the actual need, during times when processing cycles in the data storage device are available. By operating the garbage collection when the device has available processing may mitigate transition to an urgent mode.

Claims (50)

1. A controller for a data storage device, comprising:

a memory device comprising computer-readable instructions; and

a processor configured to read the computer-readable instructions that cause the controller to:

receive a plurality of commands;

train a machine learning model based on the plurality of commands, wherein the machine learning model includes a recurrent neural network (RNN) cell architecture that utilizes an algorithm that includes w xh , w hh , w hy , b h , and b y , wherein w xh is a weight between an input and a hidden layer, wherein w hh is a weight between a previous hidden layer and a current hidden layer, wherein w hy is a weight between a hidden layer and an output layer, wherein b h is a bias to calculate h [t] at time-step t and b y is a bias to calculate y [y] at time-step t, wherein:

h [t] =tan h ( h [t−1] *w hh +x [t] *w xh +b h ),

y [t] =h [t] *w hy +b y , and

y [t] =softmax( y [t] ); and

generate, with the machine learning model, a plurality of predicted commands of a host device.

2. The controller of claim 1 , the processor further configured to cause the controller to initiate a garbage collection (GC) process when a number of blocks of the memory device required by the plurality of predicted commands is below a threshold of available blocks of the memory device.

3. The controller of claim 2 , wherein the plurality of predicted commands comprise a random write pattern.

4. The controller of claim 3 , wherein the GC process is given a priority to execute before the plurality of predicted commands are received by the controller.

5. The controller of claim 3 , wherein the processor is further configured to cause the controller to receive logical block addresses (LBAs) and transfer lengths associated with the received commands, and train the machine learning model based on the LBAs and transfer lengths.

6. The controller of claim 2 , wherein the blocks are multi-level cell (MLC) blocks.

7. A data storage device, comprising:

a controller configured to perform a method for command prediction, the method comprising:

receiving a plurality of front-end command sequences from a host;

generate a plurality of symbols by mapping each of the plurality of front-end command sequences to a symbol representing a backend command, wherein generating a plurality of symbols utilizes a machine learning model that includes a recurrent neural network (RNN) cell architecture that utilizes an algorithm that includes w xh , w hh , w hy , b h , and b y , wherein w xh is a weight between an input and a hidden layer, wherein w hh is a weight between a previous hidden layer and a current hidden layer, wherein w hy is a weight between a hidden laver and an output layer, wherein b h is a bias to calculate h [t] at time-step t and b y is a bias to calculate y [y] at time-step t, wherein:

h [t] =tan h ( h [t−1] *w hh +x [t] *w xh +b h ),

y [t] =h [t] *w hy +b y , and

y [t] =softmax( y [t] );

analyzing the plurality of symbols to predict a future symbol that represents a front-end command sequence of the host; and

allocate resources of the data storage device responsive to the future symbol.

8. The data storage device of claim 7 , wherein each symbol of the plurality of symbols is aggregated to a symbol sequence.

9. The data storage device of claim 8 , wherein the analyzing comprises providing the symbol sequence to a machine learning algorithm.

10. The data storage device of claim 7 , wherein a portion of the plurality of symbols are comprised of write-symbols representing write back-end commands.

11. The data storage device of claim 10 , wherein a transfer length is associated with each of the write-symbols.

12. The data storage device of claim 11 , wherein the method further comprises analyzing the transfer length associated with each of the write-symbols with a machine learning algorithm to predict a future transfer length associated with a future symbol.

13. A data storage device comprising:

a memory means;

a controller coupled to the memory means, configured to:

receive a plurality of command sequences, at least one of the plurality of command sequences comprising a write command;

predict with a machine learning model a future write command, wherein the machine learning model includes a recurrent neural network (RNN) cell architecture that utilizes an algorithm that includes w xh , w hh , w hy , b h , and b y , wherein w xh is a weight between an input and a hidden layer, wherein w hh is a weight between a previous hidden layer and a current hidden layer, wherein w hy is a weight between a hidden laver and an output layer, wherein b h is a bias to calculate h [t] at time-step t and b y is a bias to calculate y [y] at time-step t, wherein:

h [t] =tan h ( h [t−1] *w hh +x [t] *w xh +b h ),

y [t] =h [t] *w hy +b y , and

y [t] =softmax( y [t] ); and

execute a process to make space on the memory means available for the future write command.

14. The data storage device of claim 13 , the controller further configured to:

map each of the plurality of command sequences to a symbol;

provide each symbol to the machine learning model;

receive a predictive symbol from the machine learning model; and

map the predictive symbol to the future write command.

15. The data storage device of claim 14 , the controller further configured to:

receive a transfer length associated with the write command;

provide the transfer length; and

receive a predicted future transfer length of the future write command.

16. The data storage device of claim 15 , the controller further configured to:

classify the write command as a random write command or a sequential write command based on at least two logical block addresses (LBAs) associated with the write command.

17. The data storage device of claim 16 , the controller further configured to:

classify the future write command responsive to the classifying of the write command.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2021
From: A, SHAHEED NEHAL; SINGLA, LOVISH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056518/0506 →